In my last project involving an FPGA (uCPU), I quickly noticed several limitations in the design I had developed—inadequate memory, low register count and limited branch/jump distance. I've solved the last two of these limitations with my 32-bit CPU I built in Logisim, but the first was a problem. The FPGA development board I have (miniSpartan6+) has an on-board 256Mbit SDRAM chip, which would give me a useable amount of memory. However, because it is an SDRAM, the chip's interface is radically different from a simple SRAM, so I knew that I'd have to build a controller to interface the CPU with main memory, and that was too much of a challenge to tackle at the time I was developing uCPU. Now, after a good amount of reading about SDRAM, I'm ready to take on the challenge of writing an SDRAM controller, and hopefully fitting that as well as a 32-bit (I may have to switch to 16-bit for space reasons) CPU core onto my FPGA.