BARCO NX-4 GROUP REVERSING ADVENTURE

I tried to describe this in words, but I think something was lost in translation.  Much easier with a photo.

The panel is divided into twelve segments of 16x6.  Each segment is driven by three Texas Instruments TLC5941 16-channel LED drivers.  Each driver controls one color of the tri-color LEDs.  The three drivers have their serial data cascaded, with the first controller in the cascade being Red, then Green, then Blue. 

The 96 LEDs in the segment are controlled by only 16 driver channels by multiplexing the rows' LED anode voltage (TLC5941 switches the cathode side).  Each of the 36 rows has a transistor between the panel's +4.5V input and the LED anodes.  All like-numbered rows' transistors are connected to a common control pin on the CPLD.  The CPLD cycles through them in sequence as instructed by the FPGA, synchronized with the incoming display data.

Take care when rewriting HDL for the FPGA.  Because the LEDs are expecting to be run at only 1/6 duty cycle, they may theoretically be damaged if they are not cycled as quickly by user HDL.  (For experimenting, consider using the calibration LEDs on the rear of the panel, which are not multiplexed.)

Here are some poorly-lit photos I took of the assembly.

Control Board - Front

Control Board - Rear

LED Panel - Front

LED Panel - Rear

As viewed looking at the rear of the LED panel.  The panel is arranged as a 36row x 32col grid.  LEDs are split into 16 left and 16 right columns, with every six rows driven by three cascaded drivers.  From right to left, the first driver drives Red subpixels, the second Green and the third Blue.  Anode voltage is switched to each of the six rows of LEDs in sequence via a transistor controlled by the CPLD.

There are three I2C devices on the LED panel, an EEPROM, a temperature sensor and an ambient light sensor used for brightness calibration.

Most of the LED driver control pins are brought out to the data connector by way of two buffers.  The remaining signals (SOUT for each driver string) are fed to the CPLD.

Power connector:

Data Connector:

*CPLD pins are not yet mapped to functions.  CPLD functions include cycling through rows, routing SOUT data from LED drivers, and six pins mapped to transistors scattered across the board with yet unknown function.