RISC-V Instruction Set Architecture

RISC-V at HotChips-26

The RISC-V team was out in force at the HotChips-26conference manning a sponsor booth.  Alongside a bunch of cool giveaways, including RISC-V buttons and bumper stickers, we had several demo boards at the conference. From left to right: a dual-core Rocket+Hwacha system in IBM's 45nm SOI process, running up to 1.35GHz, a single core Rocket+Hwacha system in ST 28nm FDSOI process running down to 0.45V, and an FPGA prototype running on a Xilinx Zybo board.

RISC-V on EE Times

RISC-V: An Open Standard for SoCs, the case for an open ISA has been published on the EE Times Blog. It is also available as EECS Tech Report 2014-146.