Tern - Ternary Logic Circuits

Finally! I have built and tested a fully functional true ternary SR Latch. No more cheating with sample-and-hold circuits. The basics are as one would expect. There are two inputs, Set and Reset. In this incarnation there is only one output, Q but adding a Q complement is as trivial as tapping Q with an inverter. The design uses two comparators operating as latches between + and - with a hysteresis zone between roughly -1V and 1V. One of the two latches is passed through a C gate(clamp down, - becomes -, 0 becomes 0, and + becomes 0). These outputs are then Maxed together to give a winner-takes-all final output Q. Because of the hysteresis, a 0 input results in no change. There is encoding logic in front of the two latches such that if the Set input is - then both latches are - and the output is -. If set is + then both output + (but one is clamped down to 0, important later, but the + output still wins the winner-take-all final stage). If the Set input is 0, there is no change. The Set input can change the output from any state to + or - and can even switch between them without requiring a reset. The Reset input sits at - (logically asserting no reset) generally but bringing it to + causes the un-clamped latch to go to - while the clamped latch goes to +, which is then clamped down to 0. It is now the higher of the two and the final output is 0.

Like any latch it starts in an undefined state and needs to be initialized by giving it a reset. Valid inputs are:

Set= 0 , Reset = -, Q = Q

Set = 0, Reset = +, Q = 0

Set = -, Reset = -, Q = -

Set = +, Reset = -, Q = +

I don't list any valid states for Reset = 0 because reset should logically always be asserted one way or the other. A 0 input on the reset line is invalid in this implementation because it was easier to build up a circuit with a truth table where I could simply ignore that condition. I'll post a schematic as soon as I have time to draw one. It's actually not terribly complex and only requires four chips and a bunch of resistors and diodes. One of those chips is actually just a voltage follower to provide isolation between the open collector outputs of the encoding logic and the latches which use voltage dividers to provide hysteresis. The open collector pull-up resistors mess with the voltage dividers and skew the hysteresis zone (near as I can tell). If I move the encoding logic over to components that use push-pull outputs I may be able to bring it down to only three chips.

Next step, a true Flip-Flap-Flop which would require an enable/clock input. This should be trivial.

I've been very carefully and very methodically going through every failure mode I can work out for two possible flip-flap-flop circuits. One uses two comparators as latches with a bit of encoding and decoding circuitry before and after the latches to combine their outputs appropriately. The other uses comparators for inverting purposes and is a bit more like a traditional binary NAND or NOR flip-flop. This also requires some encoding and decoding circuitry to handle the inputs correctly.

The thing I'm seeing that may be a fundamental design flaw is my voltage-to-logic mapping. It seemed quite reasonable to assign the lowest voltage a logical value of -, the intermediate voltage as 0, and the high voltage as +. This appeals to our "more is better" mindset and seems like a natural extension of existing binary logic levels. However, there is a fourth state to consider; High-Z. In a binary system, the closest logical approximation to high-z is 0, the "off" logic level and it also happens to coincide with the 0 voltage level, no voltage. In a ternary system, the closest logical approximation to high-z is also 0, the "undefined, uncertain, don't care, doesn't matter" logic level. Unfortunately, high-z is always the lowest possible voltage level which, in my case, has already been assigned to the logical negative.

This is not the kind of flaw that prevents progress or breaks the whole project, but it does cause some headaches and awkward logic. Because the assignment of a logic state to a voltage level is entirely arbitrary it would actually be a better design decision to assign the lowest voltage level to be logical 0 so that it coincides with high-z. - and + would then be the intermediate and high voltage levels.

I tested out the sample and hold IC's and they work just as I expected. However, I also had a realization that might explain why some of my previous attempts at a real latch failed. I had been testing them by hooking up the input wires to the three voltage rails, moving them from rail to rail, and watching the output on a meter. In testing the combinational circuits I've built this always worked just fine. When I started making sequential circuits I ran into trouble with unexplainable outputs that didn't match what I thought they ought to output. I knew that when I moved an input wire from one rail to another there was a period in between when there was no input voltage and I always accounted for this. Unfortunately I always thought of this "input" as being 0, just like in a binary system. Not so here! No voltage input is actually equivalent to a - input because - is the lowest possible input. All that time I was confused by inexplicable outputs, but the outputs I was expecting were wrong to begin with. I wonder how many of my previous latch designs were actually working perfectly...

Here's where I'm thinking about taking this:

1) Get some D-Latches working using sample and hold IC's.

Should be no sweat.

2) Test these out by making a variety of register and counter circuits with them.

This might be significantly harder.

3) Build and test a functioning Sum gate.

Tedious but doable.

4) Put registers and sum gates together to build a little state machine that calculates the fibonacci sequence up to 2 or 3 trits.

Hard.

The above would demonstrate a functioning truly ternary Class C machine. From my extensive research I couldn't find a single example of a true ternary machine of this complexity since they halted production of the Setun computers in 1965. The closest thing I've seen is a counting and adding machine that used two binary inputs per trit and produced ternary outputs. It was a nice demonstration of the logic, but wasn't truly ternary.

I guess I'm going to learn some analog design on this project even if I have to do it kicking and screaming the whole way. I just tested out using a single Op Amp to implement monadic P, the ternary buffer by configuring it as a voltage follower/unity gain amplifier. I also built a monadic 5, the "simple" ternary inverter with two resistors and an Op Amp configured as an inverter. I really should have learned this stuff in "Baby's First Electronics Handbook", but I never had any formal education on the subject so it was a surprise to me. This is nice because I was implementing P gates and 5 gates with two comparators, three resistors, and two diodes each.

I have also decided to stop fooling around with trying to build ternary latches out of comparators. I have successfully built all sorts of bistable circuits using feedback loops but have been unable to implement a "simple" ternary SR Latch because there is always one or more seemingly valid inputs that mucks the whole thing up. I've been close to successful with three different designs but it's just not coming together. I also don't feel too bad about it because it's actually a solved problem already. FLASH memory uses up to six different voltage levels to store multiple bits per memory element so I know it can be done. I just haven't figured out a way to do it with the materials at my disposal.

Nevertheless, I'm not going to go full dark-side and cheat with binary digital electronics (like an ADC followed by a DAC) but have instead placed an order for some sample-and-hold I/C's (LF398's specifically). These aren't true latches because they will lose their memory over time due to leakage current. If one were storing a -, it would maintain indefinitely, but a 0 or plus would droop down over time. The LF398 claims a 5mV/Sec droop rate if you use a .1uF polystyrene capacitor so if I stored a + it would take about 13 minutes to droop below the 1V threshold that would degrade it into a 0. If I stored a 0, it would only take about 3 minutes to droop below the -1V threshold that would degrade it into a -. I'm sure this is going to be irritating during design and testing, but I can't imagine anything I would prototype taking more that 3 minutes to use a stored value.

Things I've learned recently:

• Unity gain amplifiers (inverting and non-inverting) could be useful as simpler replacements for the more complex "simple" inverter and buffer that I've already built.
• You can get a High-Z output from an open collector by not using a pull-up resistor.
• Schmitt triggers are useful and easy to build.
• Analog is way more interesting than I thought.
• Application of positive and negative feedback in amplifier circuits can help you do some real sorcery.

After two months of thrashing about I finally discovered that all of the necessary prerequisites to a ternary SR "Flip-Flap-Flop" have been solved problems for decades. No time to get into it now, but it turns out that voltage comparators have been used to implement primitive analog Flip-Flops for ages. With just resistor voltage dividers you can designate the flip-up voltage and the flop-down voltage to anything you want that your comparator can handle. I've now got working examples of flip-flops that range from + to - and from 0 to - with threshold levels very close to the ones I was already using. With any luck and a bit of ternary glue-logic I'll have a realized SR Flip-Flap-Flop in short order.

Thats it. I'm selling out and moving on to hardware simulation. I have proven to myself that all monadic gates can truly be implemented with non-binary circuits and that I have a functionally complete set of components capable of building any of the 19,000 plus two-input gates. Unfortunately, I don't have the time or space to build larger and larger "pure" ternary circuits. I've looked for chips with many more comparators, I've looked at laying out custom prototyping boards, and I've looked at alternative non-binary tools like crosspoint switches to make the circuits more compact and simpler... but to no avail. The purist route is time consuming and desk-space consuming.

I've been on the prowl for simulation alternatives that don't make me feel like I'm cheating completely and I've finally found it. It's the Maxim Integrated MAX11300 "PIXI". The adorable name doesn't hurt. Basically, it's 20 pins of... analog(?) goodness. You can program it (using SPI) to configure each of the 20 pins to be a DAC, an ADC, comparator, GPIO, switch, etc. Some of those require more than one input pin or more than one output pin, but you get the idea. The possibilities are almost endless. While there is some digital magic happening in the gooey center of the chip, I can choose to only use analog inputs and outputs to ensure that my ternary purity isn't tarnished too badly. This is about as close as you can get to an analog FPGA.

The only thing I have left to prove to myself before I move on is a functional purely analog ternary latch.

So I've been working on the Sum gate off and on for a little while and it's been a tough one. First it took me a while to find a combination of monadic gates that would give me the appropriate truth table. I won't bore anyone with the details but I worked out that (2 AND B) OR (6 AND P) OR (K AND 7) would do the trick. This would only take 8 comparators if I omitted the full P gate and just used a diode in its place (P gate is just a buffer) and used wired AND's and wired OR's instead of full gates. This did work after a fashion but the breadboard became so complex that just building it without errors was time consuming.

Unfortunately, it only sort of worked. There were just too many diodes interacting with too many other diodes to get really acceptable and stable voltage levels at the final output. A "0" output might be as high as half a volt and a - could get up to -3 when it should be -5. The +'s were mostly okay, but it was a bit of a mess overall. I was definitely experiencing too much voltage drop across various groups of diodes, but I think I also ran into excessive reverse leakage current in one particular spot. Long story short, I need to replace some wired logic with more comparators to make this sucker work reliably. That means 10 or more comparators for a single gate!

I really need to find another solution that isn't just cheating with a microcontroller to simulate the ternary logic.

I was going to get to work on the Sum gate (addition of two trits) but I got distracted by latches, the most elementary possible memory device. I didn't expect something as basic as a ternary equivalent to the SR latch to be too much of a challenge, but I was very sadly mistaken. Take the lowly binary SR Latch.

Being binary, it must have two steady states. In one state, only the set pin will change it. In the other state, only the reset pin will change it. And it must have a third input state wherein no change occurs. Further, it has two outputs which are always compliments of each other.

Extending this to a ternary framework has cracked my brains. At first, I tried simply hooking up two ternary NOR gates as shown in the picture. This failed... I think. The fact is, because you have to take into account the state of the inputs (2 inputs or 3?) and the current state and next state of the Q and !Q outputs... or should there be three. Depending on how you look at it, a simple latch might have anywhere from 27 to 243 possible states. I think. Also, even if you did an exhaustive test of all possible states (I actually tried) you would end up with suspect results. Any circuit that employs multiple feedback routes can potentially have race conditions. How to know if you are measuring and recording a result that will be repeatable, or one which just happened to exit the race condition in that state?

I think I need to go back to the drawing board and see just how simplified a latching feedback circuit can get and then approach that circuit with ternary signals. Just what is the ultimate simplified memory circuit?