Tern - Ternary Logic Circuits

The equality gate outputs plus when both inputs are the same; otherwise it outputs minus. I initially thought to make this gate using a combination of two monadic 2's (+ - -), two 6's (- + -), and two K's (- - +). These could be arranged such that the gate always produces a - unless both inputs were the same. This would have required 8 comparators since 2's and K's are one comparator each and 6's use two comparators each. Instead, I worked out that, but judicious use of wired AND and wired OR I could build this gate using two P's (which can be implemented with just a couple of diodes), two A's (two comparators each), two 4's (one comparator each), and a single 2 gate (one more comparator). That comes to a total of only 7 comparators. Yay.

The P OR P gate is a Max gate

The A OR A gate (The DAD gate by my naming convention) looks like this

And the 4 OR 4 gate (DD4 gate) looks like this

If you look at these three truth tables and just take the lowest value in each position (through the use of Wired AND) you get this truth table

By passing this through a 2 gate (+ - -) the -'s get turned into +'s and the 0's get turned into -'s and you get this

And thus we have a Equality gate. One that only returns a + when the two inputs are the same and returns a - otherwise. Here is the schematic.

I've updated the schematics for the Consensus gate and the Ternary Monadic gates N-Z. Nothing important, I just noticed the page size was A4 instead of US Letter so now they are consistent with the other schematics.

Consensus is here, Monadics N-Z are here.

One of the useful properties of the binary XNOR is the fact that it is true only when both inputs are true and is otherwise false. The ternary XNOR does not share this property. A related gate does demonstrate this property and is called the Consensus Gate. The consensus gate is + when both inputs are +, is - when both inputs are -, and is 0 in all other conditions. Dr. Jones indicates that this gate is very useful in certain balanced ternary arithmetic circuits. In fact, the Consensus truth table is also the truth table of the carry-out when adding two ternary numbers. If you add two -'s you get a - carried to the next column over. If you add two +'s, you get a + carried over. Because of its usefulness in the future I'm glad it was a very simple one to build. It consists of a Min gate and a gate composed of two monadic C's OR'd together. Based on my earlier naming scheme, this two-C's-OR'd-together gate would be designated a "CDD gate" based on it's truth table. I simply took the outputs of each and OR'd the results together.

The CDD Gate, composed of two monadic C's OR'd together.

The Min Gate, composed of two monadic P's AND'ed together.

The final Consensus Gate, from OR'ing the above two gates together.

Here is the schematic.

When I first built up the XOR and XNOR gates I used the rather naive method of just copying the method used in binary of stringing together NOR gates in particular patterns. This worked just fine but totally neglected the greater flexibility inherent in ternary circuits. I worked out on paper, and just tested on the board, an XOR that is reduced from 6 comparators to only 2 comparators as well as an XNOR that is reduced from 8 comparators to just 2 comparators. They both make heavy use of wired logic to make that possible. I also changed them to use LM319's for the sake of consistency. The previous versions of XOR and XNOR used 393's.

I'm pretty jazzed about this because I'm starting to have visions of single board ternary ALU slices. Lot's more work to be done before anything like that happens though.

The schematics are here and here.

The Nonimplication gate and the Converse Nonimplication gate have been simplified with the use of Wired AND logic. Here is the updated schematic.

Further improvements. Now Antimin and Antimax can be implemented with only two comparators. Here it is.

I had tried to simplify the Min gate with Wired AND but didn't get outputs that made any sense. I assumed this was because of diode voltage drop. It's actually because I was assuming that a Wired AND Min gate would use the same monadic sub-gates as the Wired OR version. Of course that doesn't work because the different logical connective (AND vs. OR) requires a different set of inputs to get the same output. Long story short, I needed to use monadic P gates instead of monadic 5 gates in the Wired AND version. I had simply misinterpreted the unexpected outputs as a hardware defect when the problem was really "between the keyboard and chair".

Now the Min gate can be implemented with only two LM319's instead of three. I'm more than happy to spend time on all these tiny improvements because I know that component count will be of paramount importance to my ability to build more and more complex structures.

Here is the updated schematic. Again.

I'm reviewing existing schematics again and making improvements and simplifications using Wired AND logic where appropriate. So far I've added an unbuffered version of the Min gate and I believe I can make a simplified version of the AntiMin gate as well but haven't tested it yet. Simplified versions of the Nonimplication, Converse Nonimplication, and XNOR gates may also be possible but it will require a little more thought and experimentation to verify those.

Here's the updated schematic showing the new unbuffered Min gate.

The use of Wired AND has allowed me to simplify the two most complex monadic gates. Previously, the gates 7 (0 + -) and F(- + 0) were the only monadic gates that required three comparators so that they could not be built with a single LM319. With this change all monadic gates require only one 319 at the most.

The updated schematics are here and here.

For a while I've been using a pair of diodes (and a pull-down resistor to -5V) to connect the outputs of two gates together and get a combination of them. When this is done, the final output is equal to whichever gates output is higher. So far, several of the monadic gates and all of the two-input gates use this trick in order to arrange the final truth-table. This is called wired logic and is actually a "wired OR". In a binary system if one gate OR the other gate is high, the output will be high.

This can be turned around by reversing the diodes and changing the pull-down into a pull-up to +5V. This is a "wired AND". I've done a few initial tests and the result, even with three logic levels, is to always output the lower of the two gates. In other words:

Wired OR

- OR - = -

- OR 0 = 0

0 OR 0 = 0

- OR + = +

0 OR + = +

+ OR + = +

Wired AND

- AND - = -

- AND 0 = -

- AND + = -

0 AND 0 = 0

0 AND + = 0

+ AND + = +

This additional tool will make designing more complex circuits easier since I will be able to "build up" a truth table using wired OR, as well as "build down" a truth table using wired AND.

Incidentally, it occurred to me that I have developed a whole new class of digital circuits; Comparator-Diode Logic. Yay! Okay, I know a comparator is just a bunch of transistors and such, but still...