FPGA emulating MicroSD runs Google ProjectVault HDL code.
Already have an account? Log in.
To make the experience fit your profile, pick a username and tell us what interests you.
Fits into Micro-SD slot, 4 Layer PCB, Xilinx Artix FPGA A15T to A50T, Murata DCDC Regulators, SiTime MEMS oscillator, 2MByte Micron SPI Flash, NAND Flash, one LED, ambient light sensor, 10 pin extension header with 4 I/O's and JTAG (JTAG pins can be used as 3 input only pins),
Designed to run google geophyte HDL
Well it almost works with the ORP (open reference project) design from Google. Here is kinda of proof, the image is read back from the NAND flash chip visible in the front (Artix is a other side back). The NAND flash is 1 Gbit, and to big surprise Google geophyte was configured to this size, so it all worked with no changes applied.
.. and wasted full weekend. I should use F words and other words, so I want say it here.
I looked like it all could just work, but then it did not, and refused and refused and..
So until today the only code that has actually been working as SD card emu on this hadware is my own old simple code.
Google ORP code has passed a few times as much as until CMD 18 too, but got frozen in all attempts so far before coming operational.
This is amazing, I did take some old code from 2011, imported to Vivado, generated bitstream, flashed the SPI Flash with #Hack ToolZ inserted into SD Card Reader - and as soon as plugged it into the PC USB port it was recognized as Removable media with readme.txt
And changing the README.TXT would controls as example the LED on the board.. or does something else.
The best thing is that this code would also fit into #DIPSY this is COOL, id say its DIPSY.COOL !
README.TXT is coming from FPGA Block RAM !
Quiz how many BGA packages total?
Answer: 5 !
The first board, well I managed to place the FPGA 180 degrees wrong. The second board was assembled today and this time all components are OK. All so far working too.
First actual use, microSD Artix is logging the SD Card init boot sequence of the ZYNQ Bootrom
The actual PRODUCT of interest is that small board in the microSD Adapter, at the other side is Artix A35T the red wires going to the right are JTAG.
This the "code" in the FPGA, 6 pins connected to ILA = Integrated Logic Analyzer
First SD Commands are visible.
This design uses all ready Vivado IP Core Catalog stuff, no manual coding done at all.
Partial hand assembly without stencil, there is one tombstone. the part in the front is optional it is hard to get right without stencil so it is not assembled at all. The shiny part is chipscale spi flash, it is really low height too.
The GOLDEN area is defined by UHS-II spec as "cooling" area for heat transfer from microSD card to the socket and main PCB.
There seems to be no direct stock availability in Europe for A50T, but we should get some A35T samples to test the board. Waiting in excitment.
pushed to github all hardware CAD source files and generated files too
While waiting for the microSD Artix board, will start Zynq porting of the geophyte SD emulation code using this adapter setup
Soft Propeller Zynq DIP module is inserted into small adapter board that fits the pin header in old old SD Card break out board.
After some more fix of the clearances the PCB fab is ready to start production!
The green parts are the DCDC converters from Murata. Left small device is SPI Flash, the largest part is NAND, in the right back is the Si1143 sensor, and IR LED (pictured as red, but it is clear actually).
we have a very limited amount of working units. I check next week what we can do..
Can I order two please? My former roommate worked on the ATAP project (he did the OS for google's reference impl)
Depends on design, it can be below 200mW. If you look the 3D rendering, then there is visible FREE COPPER area, this is taken from SD UHS-II specication where this are is for cooling and thermal transfer from Card to the Socket and main board.
Antti Lukats
vishal soni
Adam Billingsley
Ziv Barcesat
It looks like you have a 22µF ceramic capacitor. Considering that the capacitance of an MLCC will decrease with voltage applied, it is only a fraction of the 100µF recommended in the 7 Series FPGAs PCB Design Guide (UG483). How did you know it was enough?