Close
0%
0%

FPGA computer

I am building a (currently) 64k RAM computer with an FPGA. Now with lots of pipelining!

dylan-brophyDylan Brophy
Following
Liked Like project

Just one more thing

To make the experience fit your profile, pick a username and tell us what interests you.

Pick an awesome username
hackaday.io/
Your profile's URL: hackaday.io/username. Max 25 alphanumeric characters.
Pick a few interests
Projects that share your interests
People that share your interests

We found and based on your interests.

Choose more interests.

OK, I'm done! Skip
Similar projects worth following
3.7k views
4 comments
39 followers
View Gallery
My goal for speed is 133 MHz. It has a custom 16-bit processor architecture. Peripherals currenty are UART, SPI and 8 LEDs.

With my NGT20 I have VGA output working.

USB/PS2 keyboard is supported.

New Planned Specs

New architecture that leans more toward RISC, but has many similarities to x86 architecture.

  • 64-bit
  • 4 general purpose registers
  • 2 pointer registers
  • should be ABSURDLY FAST (for an FPGA)
  • Still in the works....

Old Specs for early N016 CPU

This cpu was my first ISA design, and really had serious problems with speed. It simply did too much per clock cycle and had a ridiculous number of instructions. Studying the Z80 taught me a lot about good performance.

This FPGA computer, so far, has:

  1. 2 clock inputs
  2. UART input/output (for communication with graphics card)
  3. CPU, also work in progress
  4. a 31-bit timer
  5. very basic BIOS to load program from disk, will be improved
  6. PS2 Keyboard support

I am going to add:

  1. Operating system
  • Specs so far
  1. 16-bit CPU
  2. 50MHz (could probably run at 100MHz with even more pipelining)
  3. Only ROM for now since I'm still getting hardware going good

  • 1 × Any FPGA board w/ VGA, UART, and PS2 keyboard Digilent spartan-3a stater board or better recommended.

  • New CPU design, mass storage problems

    Dylan Brophy • 04/02/2017 at 20:40 • 0 comments

    My old N-Series CPU design is an incredibly inefficient CISC architecture that is no doubt super slow just due to the number of clock cycles and unnecessary memory accesses per instruction. I'm going to create a new architecture that supports more memory and is hopefully much faster (133 Mhz???).

    The reason I haven't updated this project much in so long is because I ran into some mass storage problems. The FPGA board I'm using has 3 places to store non-volatile data. After an attempt at every. single. one, I needed a break. Its a bit frustrating when not even parallel NOR flash will work right, after trying SPI eeprom and the FPGA's own non-volatile storage. Any advice would be appreciated, by the way.

  • PS2 Keyboard interface working

    Dylan Brophy • 10/02/2016 at 09:34 • 0 comments

    I finally got the keyboard to work. PS2 interface working nicely and printed keystrokes on the screen. I was getting trouble when using my FIFO as a hardware keyboard buffer, needed to fix some timing. Also now working on a sort of datasheet for my CPU, I'll make docs for the entire system when it has disk support.

  • Video working, and new interface too!

    Dylan Brophy • 08/01/2016 at 01:32 • 0 comments

    I eventually decided that putting graphics on the FPGA would not be a good idea for two reasons:

    1. The CPU would be drawing the graphics
    2. I would only have enough memory for 8-color 256 x 256 pixel graphics

    This just wasn't going to be enough, so I brought in my Parallax Propeller chip. The propeller is perfect because it runs on 3.3v, has great ability to generate graphics, and will do the video processing for the main CPU. I set it up with UART at 115200 bps and connected it to my FPGA. It took some trial-and-error to get some signs of life from my Propeller saying that it was getting a transmission, then from there I got a Hello World program working.

    From here I decided that between the FPGA and the other devices there will be a standard protocol using UART. Don't worry, the UART won't be as slow because there are hardware FIFOs allowing a program to run without waiting for data to finish transmtting.

  • Redesigned layout in ISE

    Dylan Brophy • 08/01/2016 at 01:04 • 0 comments

    I decided things should work better if I broke my project into mini projects, tested them, and included them into the main project. This seems to have worked very well. I also made this change so that if I made another version of the design in another ISE project, It would be easy to make backwards compatible and\ work together.

View all 4 project logs

Enjoy this project?

Share

Discussions

ProvidenciBins wrote 07/16/2020 at 05:43 • point

I have seen the structure and design of your created FPGA computer which is absolutely appreciable. I like to visit gamblizard.com/deposit-bonuses/200-casino-bonus source for 200% Deposit Bonuses.I have to say that you can increase the speed more than the 133MHZ by introducing some required changes.

  Are you sure? yes | no

f4hdk wrote 04/01/2017 at 08:42 • point

Nice project. 

But why don't you use more ram? 64k for a 16bits computer, that's very little. 

Of course, it depends on what you want to do. But you are talking about OS and graphics, which both consume RAM space.

  Are you sure? yes | no

Dylan Brophy wrote 04/01/2017 at 15:13 • point

That is a good thought. I will look into that.  I would probably change my CPU architecture to have some 32 bit registers, then connect more adress lines.

  Are you sure? yes | no

Marq Watkin wrote 04/01/2017 at 20:25 • point

This project sounds quite like something I was planning, so I'm interested in what you come up with.

You could skip the need for 32bit registers by implementing a banking system.

For example, you have an 8bit (or even 16bit) "bank" register, and you alter the value by an opcode. This is then used as your higher address lines for RAM.

The only thing with this approach, is I'd recommend defining your banks as 32k, with the lower 32k is always fixed to a single block of RAM, and have the upper 32k be the switchable banks. This way, your application loop can run within the lower 32k loading in functions and data across the banked RAM so you can utilise it all.

If you use the 8bit bank register, you could support around 8MB RAM, which should be pretty useful.

I hope I explained it well, if not, have a look at how the Gameboy supports memory banks so you have have games over the tight restrictions in that

  Are you sure? yes | no

Similar Projects

A journey to discover what it's like to build your own processor.
Project Owner Contributor

Holy Nonads! A Nine-Bit CPU!

mad-nedMad Ned

A custom 32-bit CPU core with GCC toolchain
Project Owner Contributor

Bexkat1 CPU

matt-stockMatt Stock

The Kestrel project is all about freedom of computing and the freedom of learning using a completely open hardware and software design.
Project Owner Contributor

Kestrel Computer Project

samuel-a-falvo-iiSamuel A. Falvo II

Retrochallenge 2016/10 entry and winner: try to build a TI-99/4A clone using a TMS99105 CPU and an FPGA. In a month...
Project Owner Contributor

RC2016/99: TI-99/4A clone using TMS99105 CPU

erik-piehlErik Piehl

Does this project spark your interest?

Become a member to follow this project and never miss any updates

By using our website and services, you expressly agree to the placement of our performance, functionality, and advertising cookies. Learn More

Yes, delete it Cancel

Report project as inappropriate

You are about to report the project "FPGA computer", please tell us the reason.

Send message

Your application has been submitted.

Remove Member

Are you sure you want to remove yourself as a member for this project?

Project owner will be notified upon removal.