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Flip-Flop Test Jig
09/27/2015 at 06:27 • 1 commentThe jig to test the flip-flops has been finished:
The jig is basically an Arduino Mega 2560 and a Protoshield. Press the 'GO' button and the flip-flop under test is checked for /RST, /SET, D->Q, and output tristate functionality. I've tested the 18 flip-flops I made earlier and found 4 failures - more than I'd like. But the jig indicates at what point in the testing that the failures fail so troubleshooting shouldn't be too difficult. And I have 14 which are ok!
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Address Decoders for Stack Memories
09/22/2015 at 08:48 • 0 commentsThe Data and Return Stacks will each consist of a 64-byte ferrite core array. 64 bytes requires a 6-bit pointer to address the stack contents. This 6-bit pointer must be decoded to select one of 8 columns and 8 rows in the core matrix.
Below is a closeup of some of the edge connectors I will be using throughout this project. They are 44-pin Multibus II connectors from Digikey:
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D-Type Flip-Flops ready for testing
09/18/2015 at 00:26 • 10 commentsThe first in a series of logic modules has been completed: a D-type flip flop with asynchronous SET and CLEAR, and tristateable output. It is a 6 NAND-gate arrangement similar to the 74S74. The PCB is 4 layers, and the transistors are MMBT3904s with BAT54 Baker clamps.
I've simulated it with LTSpice and it should be capable of a least a couple of MHz.
This is Rev B. Rev A worked, but I decided to make the module sides slightly concave to assist insertion and removal, and to curve the top - I think it looks nicer. I also decided to go for an edge connector - the 44-pin Multibus II.
And yes, that is a kludge wire near the top!
Here are 18 waiting to be tested:
The PCBs were made by pcbway.com. I had a kapton stencil made by OSH Stencils. I did the reflow soldering in an old toaster oven controlled by a Zallus Oven Controller.
Now I need to build a jig to test them!