The third answer in the linked stack exchange post suggests that it might be possible to make a latch with one transistor .The idea is that logic values are represented by presence or absence of a specific frequency oscillation instead a high or low voltage.
Is this actually possible? If it is, can you build digital logic based on this technique. Can it be simpler than conventional transistor transistor logic?
This would be similar to "code golf" where you try to write the shortest program to do something.
Probably a quixotic search, but I think I'll learn a lot about transistor math in the process.
A separate project that is interesting to me is to make a microprocessor with a minimal number of transistors. Wikipedia says that an 8080 has about 4500 transistors. Can that be substantially decreased? If you take out some of the features like interrupts and BCD is it possible to use fewer (performance be damned).
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Patent-US3811076.pdf
This is a patent from 1973 creating a memory chip from one transistor and one capacitor per bit.
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03/28/2018 at 20:16
I was researching early computer technology and found references to a circuit used by some Japanese systems called the Parametron https://en.wikipedia.org/wiki/Parametron It resembles some of my ideas for this circuit. I had been thinking that the circuit would represent 1 vs. 0 by the phase of an oscillating signal with 180 degrees apart would be the 1 and 0 values.
One advantage of the parametron design was that it was more reliable than early transistors.
Actually this project was already solved in 1973 by my dad! Patent https://patents.google.com/patent/US3811076 is for a memory chip made from one bit latches containing one FET transistor and 1 capacitor/
This is one possible waveform for voltage on the latch's main capacitor. The idea is that the high (red) and low (blue) values are 180° out of phase from each other. The power signal provides the concept of phase.
There has to be at least an additional capacitor or inductor to distinguish the state when the two waveforms cross each other.
[I put this in description instead of project log. moving it here]
While brainstorming, I thought of a potential implementation. The signals would oscillations 180 degrees out of phase to represent zero and one instead of yes oscillation/no oscillation.
Another brainstorming idea is to make the power supply oscillate at twice the speed of the data's oscillation. Most probably the polarity of the supply wouldn't go from + to - . Instead it would be offset from zero by a volt or two. For example, Peak to peak might between 1V and 4V.
This is a working design, but it will most likely need further improvement, especially when you want high speed.
How does it work ?
A 5 volt (TTL) clock is needed, that is in common for all latches, and present all the time. I used 3 kHz.
The output has two states:
1) in the OFF state, the 5V clock signal is strongly attenuated by the 6K8 resistor and the 3K3 - C2 combination. The signal on the base of the transistor is below 0.6 Volt, so the transistor stays off (output high, LED off).
2) The latch can be put in the ON state by shortly applying a 5V pulse to C2 via a series resistor. This will change the operating point of the transistor. The DC voltage on C2 will provide a bias voltage to the base, and the transistor will now amplify the clock signal. So, in the ON state, the output has the clock signal, the LED will be ON. The output signal will be rectified by the C1 - D1 combination, and the resulting DC voltage will appear on C2. This closes the positive feedback loop, and the latch will stay in the ON state. However, the DC on C2 could be so high that the transistor is ON all the time, and that would remove the positive feedback signal. To prevent this effect, D2 is added. Each time the output of the transistor is low, it will discharge C2. When the circuit is properly dimensioned, D2 could also act as a Baker clamp to prevent saturation of the transistor.
You can bring the latch back to the OFF state by discharging C2, or by shortly removing the clock signal.
If you want the latch to be fast, you should make C1 and C2 smaller, and use a clock that is a few times faster than the maximum operating speed of the latch.
Yes, I just simulated this in LTspice, and it works! I used the initial condition at the node between C1 and D2 to set the state of the latch at the beginning of simulation. If it's on, it stays on, and if it's off, it stays off. Very nice!
What about using both AC and DC supplies? This is how #The Diode Clock works, for example - it uses an RF power supply with DC bias controlling PIN diodes (1N4007s). Maybe you could make a one-transistor latch along the same lines as the old one-transistor reflex radios, where the same transistor amplified both RF and audio?
Hi Bill,
inspired by your project and the answer from Ted Yapo, I did build the following on a breadboard:
http://www.enscope.nl/rrca/ideas/single_npn_latch.png
This is a working design, but it will most likely need further improvement, especially when you want high speed.
How does it work ?
A 5 volt (TTL) clock is needed, that is in common for all latches, and present all the time. I used 3 kHz.
The output has two states:
1) in the OFF state, the 5V clock signal is strongly attenuated by the 6K8 resistor and the 3K3 - C2 combination. The signal on the base of the transistor is below 0.6 Volt, so the transistor stays off (output high, LED off).
2) The latch can be put in the ON state by shortly applying a 5V pulse to C2 via a series resistor. This will change the operating point of the transistor. The DC voltage on C2 will provide a bias voltage to the base, and the transistor will now amplify the clock signal. So, in the ON state, the output has the clock signal, the LED will be ON. The output signal will be rectified by the C1 - D1 combination, and the resulting DC voltage will appear on C2. This closes the positive feedback loop, and the latch will stay in the ON state. However, the DC on C2 could be so high that the transistor is ON all the time, and that would remove the positive feedback signal. To prevent this effect, D2 is added. Each time the output of the transistor is low, it will discharge C2. When the circuit is properly dimensioned, D2 could also act as a Baker clamp to prevent saturation of the transistor.
You can bring the latch back to the OFF state by discharging C2, or by shortly removing the clock signal.
If you want the latch to be fast, you should make C1 and C2 smaller, and use a clock that is a few times faster than the maximum operating speed of the latch.