Kilsyth is a piece of hardware that contains an FPGA (Lattice ECP5) and a SuperSpeed USB 3.0 FIFO-bridge (FT60x). The goal is to provide a platform to be able to transfer high speed data transfers between a PC and an FPGA. The FPGA in turn can do whatever - e.g. interface with SDR, video capture, act as a logic analyzer.
This project has not gotten a lot of my attention since I made the first rev and initial bringup.
However, people seem to find their way here and I thought I'd just leave a note about the current status of the project.
This board was designed in a rush, in order to get it done for 35C3, 2018-12-27. The goal was to have a cheap ECP5 board with a high speed PC interface and a bunch of IOs.
What is working?
ECP5 FPGA works
It can be configured through JTAG.
Clock input from FT600 and oscillator works.
SDRAM works.
Have tested a LiteX build using SDRAM and micropython.
FT600 interface works
Can make transfers to and from the FPGA at maximum speed that the FT600 can handle, i.e. 200 MB/s.
USB-C connector and routing works, however it's a pain to solder since the pads are small and it has a row of hidden pads behind the outer row. Found a different connector with pins for the hidden row instead, UJ31-CH-31-SMT-TR. Have tried it and it is much easier to rework.
What needs to be fixed?
FT_CLK is not routed to a clock input
The JTAG connector has a weird pinout.
Pin 33 on the wide connector is NC on the 12F variant
Flash needs pull-resistors.
Improve routing for high speed IOs. Even if no high speed connector is used, the signals should be routed and exposed together (A and B pins from the FPGA).
Software?
Started working on a migen project that was supposed to expose an easy way to communicate with the FPGA at high speeds.
Initial code sort of works but relies on the proprietary drivers which is a pain.
Still requires the fpga to be programmed through JTAG. Need a bootloader that loads the bitstream to flash and boots into it.
Got bored and haven't made any significant progress in a while.
RevB
I started working on a RevB but haven't really done any progress since I got stuck trying to figure out which high speed connectors to use. HDMI, SATA, USB-C, SYZYGY ...
At this point this project is pretty much on hold indefinitely. I started a dedicated HDMI capture/transmit project here, however after I learned about the Camlink and the reverse engineering progress that has already been made with that, there is no point in continuing that project.
However!
I made another board for 36C3, 2019-12-27, called pergola. That project is very much alive, please check it out instead. hackaday.io project page.
I noticed in your older board files you are escaping many of your traces at 4mil width. Is there an affordable board house that will do those tolerances? (enough to fully escape a .8 mm ECP5-256 ball)
Good to know they perform much better than their specs. Thanks!
Looking at the (unfinished) Rev.B hardware files in your repo, the .8 mm BGA pitch minus the .45 mm finished dog-bone via diameter minus the 5 mil (.127 mm) escape trace divided by 2 leaves .1115 mm or 4.39 mil via-to-trace clearance - which violates JLC's capabilities by a LOT (5 mil trace to trace clearance / .245 mm (9.6 mil) via-to-trace).
As you can see, we get 3.5 mil minimum width and spacing, 5 mil via-to-trace and so on. Rev B will be completely redesigned, the PCB file should be ignored for the time being. But Rev A has been ordered, built and tested 2018-12 and I didn't have any PCB-related issues.
I noticed in your older board files you are escaping many of your traces at 4mil width. Is there an affordable board house that will do those tolerances? (enough to fully escape a .8 mm ECP5-256 ball)