Debouncing the pushbuttons is fine but what we really need for most of the pushbuttons from a front panel is toggling lines. When a button is pressed it should toggle the state of the bit that was pressed.

Got this working and created a branch in GitHub. This uses the same IOP16 program (FP01_LOOP2) as the previous log. It still loops back the toggled pushbuttons back to the LEDs.

And it works.

The last log resulted in a loopback of the pushbuttons to the LEDs. There's no switch debouncing. 

This step will add switch debouncing to the pushbuttons. It will still do loopbacks (baby steps), but the pushbuttons will be debounced.

It would be helpful to know when the scan is completed. This will also reduce the effort to debounce since the switches are read every ~1 mS. To do this, a signal should be sent to the peripheral bus. A single write to a defined address should do the job.

IOP16 Memory Map

The SCAN STROBE address signals a frame was just scanned.

Created a new branch which latches the pushbuttons every scan. It runs the code FP01_LOOP2. The result is still not debounced, but the 32-bits of pushbuttons are latched every frame.

Debouncing

Debouncing consists of counting the number of consecutive frames the button is pressed. With an ~1 mS frame rate that would be a count of maybe 50 or so. That's long enough for the switches to settle and short enough that the delay time is reasonable.

A six bit counter would be 64 mS. Seems about right. Start the counter when the button is pressed. Reset the counter if the pushbutton is un-pressed (or still bouncing).

Created a new branch with the debounced pushbuttons. It runs the same FP01_LOOP2 code.

I got the IOP16 running and controlling the front panel.

It's currently looping back the pushbuttons to the LEDs. Here is the timing diagram for the I2C transfer (pair).

I2C Transfer - Read Pushbutton/Write LEDs

That's < 200 uS for read/write cycle.

Reads 4 banks, writes 4 banks in < 800 uS. Faster than 1 mS refresh rate. - better than the human eye. Good enough. 400 KHz transfers work at 3.3V (and 5V of course).

Created a branch in GitHub with the loopback working. If that's all you need, that will work. Push a button, turn on an LED. No debouncing of the pushbuttond, etc.

The firmware the IOP16 runs is FP01_LOOP1.

Only needs 587 logic elements, 312 registers, and 32KB of internal SRAM,

Captured the initialization code. Running at 100 KHz SCL and 3.3V power supply.

Alternating pattern on the LEDs

Initialization code is 837 instructions long. Hard coded to put alternating pattern on LEDs.

...

MIF File

-- File: C:\Users\HPz420\Documents\GitHub\Doug Gilliland\MultiComp\MultiComp_On_RETRO-EP4CE15\FrontPanel01\IOP16_ASSEMBLER\FP01_HLL\FP01_HLL_out.mif
-- Generated by pyAssemble_IOP16.py
-- 
DEPTH = 837;
WIDTH = 16;
ADDRESS_RADIX = DEC;
DATA_RADIX = HEX;
CONTENT BEGIN
0: 7905 2048 7004 6705 8701 DFFE 7805 2100;
8: 7104 6705 8701 DFFE 2103 7105 21FF 7104;
16: 6705 8701 DFFE 7905 2048 7004 6705 8701;
24: DFFE 7805 2101 7104 6705 8701 DFFE 2103;
32: 7105 2100 7104 6705 8701 DFFE 7905 2048;
40: 7004 6705 8701 DFFE 7805 2102 7104 6705;
48: 8701 DFFE 2103 7105 21FF 7104 6705 8701;
56: DFFE 7905 2048 7004 6705 8701 DFFE 7805;
64: 2104 7104 6705 8701 DFFE 2103 7105 21FF;
72: 7104 6705 8701 DFFE 7905 2048 7004 6705;
80: 8701 DFFE 7805 2105 7104 6705 8701 DFFE;
88: 2103 7105 2100 7104 6705 8701 DFFE 7905;
96: 2048 7004 6705 8701 DFFE 7805 2106 7104;
104: 6705 8701 DFFE 2103 7105 2100 7104 6705;
112: 8701 DFFE 7905 2048 7004 6705 8701 DFFE;
120: 7805 2108 7104 6705 8701 DFFE 2103 7105;
128: 2100 7104 6705 8701 DFFE 7905 2048 7004;
136: 6705 8701 DFFE 7805 210A 7104 6705 8701;
144: DFFE 2103 7105 2104 7104 6705 8701 DFFE;
152: 7905 2048 7004 6705 8701 DFFE 7805 210B;
160: 7104 6705 8701 DFFE 2103 7105 2104 7104;
168: 6705 8701 DFFE 7905 2048 7004 6705 8701;
176: DFFE 7805 210C 7104 6705 8701 DFFE 2103;
184: 7105 21FF 7104 6705 8701 DFFE 7905 2048;
192: 7004 6705 8701 DFFE 7805 2115 7104 6705;
200: 8701 DFFE 2103 7105 2155 7104 6705 8701;
208: DFFE 7905 204A 7004 6705 8701 DFFE 7805;
216: 2100 7104 6705 8701 DFFE 2103 7105 21FF;
224: 7104 6705 8701 DFFE 7905 204A 7004 6705;
232: 8701 DFFE 7805 2101 7104 6705 8701 DFFE;
240: 2103 7105 2100 7104 6705 8701 DFFE 7905;
248: 204A 7004 6705 8701 DFFE 7805 2102 7104;
256: 6705 8701 DFFE 2103 7105 21FF 7104 6705;
264: 8701 DFFE 7905 204A 7004 6705 8701 DFFE;
272: 7805 2104 7104 6705 8701 DFFE 2103 7105;
280: 21FF 7104 6705 8701 DFFE 7905 204A 7004;
288: 6705 8701 DFFE 7805 2105 7104 6705 8701;
296: DFFE 2103 7105 2100 7104 6705 8701 DFFE;
304: 7905 204A 7004 6705 8701 DFFE 7805 2106;
312: 7104 6705 8701 DFFE 2103 7105 2100 7104;
320: 6705 8701 DFFE 7905 204A 7004 6705 8701;
328: DFFE 7805 2108 7104 6705 8701 DFFE 2103;
336: 7105 2100 7104 6705 8701 DFFE 7905 204A;
344: 7004 6705 8701 DFFE 7805 210A 7104 6705;
352: 8701 DFFE 2103 7105 2104 7104 6705 8701;
360: DFFE 7905 204A 7004 6705 8701 DFFE 7805;
368: 210B 7104 6705 8701 DFFE 2103 7105 2104;
376: 7104 6705 8701 DFFE 7905 204A 7004 6705;
384: 8701 DFFE 7805 210C 7104 6705 8701 DFFE;
392: 2103 7105 21FF 7104 6705 8701 DFFE 7905;
400: 204A 7004 6705 8701 DFFE 7805 2115 7104;
408: 6705 8701 DFFE 2103 7105 21AA 7104 6705;
416: 8701 DFFE 7905 204C 7004 6705 8701 DFFE;
424: 7805 2100 7104 6705 8701 DFFE 2103 7105;
432: 21FF 7104 6705 8701 DFFE 7905 204C 7004;
440: 6705 8701 DFFE 7805 2101 7104 6705 8701;
448: DFFE 2103 7105 2100 7104 6705 8701 DFFE;
456: 7905 204C 7004 6705 8701 DFFE 7805 2102;
464: 7104 6705 8701 DFFE 2103 7105 21FF 7104;
472: 6705 8701 DFFE 7905 204C 7004 6705 8701;
480: DFFE 7805 2104 7104 6705 8701 DFFE 2103;
488: 7105 21FF 7104 6705 8701 DFFE 7905 204C;
496: 7004 6705 8701 DFFE 7805 2105 7104 6705;
504: 8701 DFFE 2103 7105 2100 7104 6705 8701;
512: DFFE 7905 204C 7004 6705 8701 DFFE 7805;
520: 2106 7104 6705 8701 DFFE 2103 7105 2100;
528: 7104 6705 8701 DFFE 7905 204C 7004 6705;
536: 8701 DFFE 7805 2108 7104 6705 8701 DFFE;
544: 2103 7105 2100 7104 6705 8701 DFFE 7905;
552: 204C 7004 6705 8701 DFFE 7805 210A 7104;
560: 6705 8701 DFFE 2103 7105 2104 7104 6705;
568: 8701 DFFE 7905 204C 7004 6705 8701 DFFE;
576: 7805 210B 7104 6705 8701 DFFE 2103 7105;
584: 2104 7104 6705 8701 DFFE 7905 204C 7004;
592: 6705 8701 DFFE 7805 210C 7104 6705 8701;
600: DFFE 2103 7105 21FF 7104 6705 8701 DFFE;
608: 7905 204C 7004 6705 8701 DFFE 7805 2115;
616: 7104 6705 8701 DFFE 2103 7105 210F 7104;
624: 6705 8701 DFFE 7905 204E 7004 6705 8701;
632: DFFE 7805 2100 7104 6705 8701 DFFE 2103;
640: 7105 21FF 7104 6705 8701 DFFE 7905 204E;
648: 7004 6705 8701 DFFE 7805 2101 7104 6705;
656: 8701 DFFE 2103 7105 2100 7104 6705 8701;
664: DFFE 7905 204E 7004 6705 8701 DFFE 7805;
672: 2102 7104 6705 8701 DFFE 2103 7105 21FF;
680: 7104 6705 8701 DFFE 7905 204E 7004 6705;
688: 8701 DFFE 7805 2104 7104 6705 8701 DFFE;
696: 2103 7105 21FF 7104 6705 8701 DFFE 7905;
704: 204E 7004 6705 8701 DFFE 7805 2105 7104;
712: 6705 8701 DFFE 2103 7105 2100 7104 6705;
720: 8701 DFFE 7905 204E 7004 6705 8701 DFFE;
728: 7805 2106 7104 6705 8701 DFFE 2103 7105;
736: 2100 7104 6705 8701 DFFE 7905 204E 7004;
744: 6705 8701 DFFE 7805 2108 7104 6705 8701;
752: DFFE 2103 7105 2100 7104 6705 8701 DFFE;
760: 7905 204E 7004 6705 8701 DFFE 7805 210A;
768: 7104 6705 8701 DFFE 2103 7105 2104 7104;
776: 6705 8701 DFFE 7905 204E 7004 6705 8701;
784: DFFE 7805 210B 7104 6705 8701 DFFE 2103;
792: 7105 2104 7104 6705 8701 DFFE 7905 204E;
800: 7004 6705 8701 DFFE 7805 210C 7104 6705;
808: 8701 DFFE 2103 7105 21FF 7104 6705 8701;
816: DFFE 7905 204E 7004 6705 8701 DFFE 7805;
824: 2115 7104 6705 8701 DFFE 2103 7105 21F0;
832: 7104 6705 8701 DFFE E344;
END;

Designed a custom I/O processor (IOP) in VHDL. Runs autonomously from the Host CPU. 

8 Bit CPU Application

The 32 LEDs can be used to monitor

• 16-bits of instructions
• 8 - bits of data
• 8 status lines (Run, etc)

The 32 pushbuttons can be used for:

• 16-bits of address
• 8-bits of data
• 8 control lines (Run/Halt, Examine, Deposit, etc)

IO Processor (IOP) Block Diagram

IOP Features

• 16-bit instruction
  • 4-bit opcode
  • 4-bit register select
  • 8-bit address/offset
• I/O Memory Interface
  • 8-bits of data (in/out)
  • 8 address lines
  • Read/Write strobe
• 3 bit grey coded state counter running at 50 MHz
• 50 MHz/8-bits/instruction = 6.25 MIPs (plenty fast enough for I/O)

Instruction Format

Assembler Input Format

CSV file with constrained input format. Header must match the example.

Compiler Input Format

CSV file with constrained input format.

First line WR001 compiles to:

Listing file:

I/O Map