Project Logs

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• Final Update

  Jesse Farrell • 08/09/2022 at 01:13 • 0 comments

  Final design works with some minor caveats (had to bodge two workarounds). The whole design process, validation and theory of operation is outlined in the HAS included in the project documents. All documentation that I plan on uploaded has been pushed. I have not pushed any gerbers since I doubt anyone will actually fab this.

  This design has been a bit of a time sink but I’m glad I have a finished widget at the end of all it. I improved my hardware debugging along the way, and got a lot better at hand soldering SOP packages…

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  Anyways here is the widget counting in slow motion  : ) 

  If you have any questions feel free to poke around the documentation for this project, or drop a comment.

• Its ALIVE

  Jesse Farrell • 07/10/2022 at 01:26 • 0 comments

  We've passed the smoke test! I’ve found a few minor errors, but nothing that can’t be worked around. I’ll go over any changes in the next project log. An example of the timer counting is shown below. In the video I show the timer being set to some arbitrary value and then enabled via a dip switch.

  Here's a better view of the design.

• Boards Ordered

  Jesse Farrell • 06/03/2022 at 19:06 • 0 comments

  Just a quick update, all the boards have arrived, and I had JLC assemble 2x of them to save me some time. I’ll be running some automated test benches on each board this weekend (assuming I don’t run out of parts).

  Here is a video for the BCD counter and BCD decoder toggling a 7 segment digit. I'll be doing more rigorous validation later.

• Project Update – New PCB

  Jesse Farrell • 05/05/2022 at 23:30 • 0 comments

  Finished my final exams so I’m able to come back and hopefully finish up this project. Previously I validated all the hardware, so I just need to implement the changes onto some new boards.

  The final widget is going to have 1 main board, and several daughter boards that slot in via headers. I’ve done 2/6 boards so far and plan to finish up this weekend. I’ll be using JLC’s smt assembly to conserve my sanity.

  Here’s the finished main board to give you an idea of the design. The weird shape of the PCB is to help it slot into a case I'm making.

• Validation – BCD Counter

  Jesse Farrell • 04/06/2022 at 22:57 • 0 comments

  The BCD counter schematic and PCB is shown below. 

   The circuit worked as expected after correcting the flip flop elements with the changes mentioned in a previous log. Note that this circuit boots into a potentially invalid state, outside the BCD range 0-9. This was anticipated and should be managed by the circuit.

  Below is a capture of the waveform powered up with the carry in bit held high. Notice as expected we booted into an invalid state (0b1111 = 15), but the next time the counter rolls over it starts at 9. The scope waveforms are organized MSB -> LSB.

  Next testing the circuit with the carry in bit = 0, we expect no roll over when the counter hits 0. A capture of this is shown below. As expected when there the carry in bit is 0, the counter doesn’t rollover.

  After some usage the solder joints on the SMD-THT bodge job (see below) began to cause some issues. Both the CLK_OUT functionality and CARRY_OUT pins were verified but no captures were taken. CLK_OUT is pulled low when all bits in the counter are 0. CARRY_OUT is high so long as any of the bits are 1.

  It might be a good idea to add a buffer between the OR gates and the Flip flop inputs. If a 555 and gate is used a reset functionality could be added to help mitigate the invalid starting state previously mentioned. 

• Validation - BCD to 7 Segment Decoder

  Jesse Farrell • 03/18/2022 at 20:37 • 0 comments

  The BCD to 7-segment decoder circuit schematic and PCB are shown below.

  Two errors were found in the decoder circuit. When translating the LTspice circuit to KiCad I mislabeled the NOR gates as XOR, leading to incorrect row 00, and column 00 decoding. The second error was an extra dependency for element B of the seven segment display (shown below).

  After soldering a 74 series NOR gate into the circuit (to bypass the XOR gates), and removing the OR gate shown above, the circuit worked as intended. Two digits are shown below. Note that some elements are dim since I’m looking at the unbuffered outputs of the logical blocks, before the flip flops (so some have 2k to GND, others are driven directly by a 555 output).

  One more error was found while working on the final board layout, I managed to flip create a backwords 6 "∂". I've correct this logic and reran the simulation.

• Validation – MUX

  Jesse Farrell • 03/11/2022 at 21:31 • 0 comments

  The 555 MUX schematic and pcb are shown below. 

  I managed to flip the inverting and none-inverting inputs of all the 555 AND gates of this circuit. Luckily, this circuit is simple enough, so I’m not very concerned about its validation. I was still able to confirm its basic functionality even with the aformentioned pin mixup. One thing I was curious about was its propagation delay.

  
  Overall, my MUX and BCD-7 Segment decoder need to be able to update within the period of the refresh clock signal (expecting to use 700Hz, so 1.4ms overall propagation delay is tolerable). The worst case propogation delay for this mux is theoretically ~15us x 5 = 75us (based on perivous validation). The observed delay was only ~5us. 

  I also tested the circuit with a 10k pull down (originally 2.2k) to see if I could reduce the forward voltage of the diode. This decreased the forward voltage by about 100mV (see images below), so not particularly noteworthy. However, increasing to 10k also increased the discharge of the diode diffusion capacitance seen on the right image below. I will keep using the 2.2k here for the final design.

• Validation - Buzzer

  Jesse Farrell • 03/06/2022 at 01:14 • 0 comments

  The buzzer circuit schematic and pcb are shown below.

  This circuit worked well for several minutes, but then began to misbehave. After about a minute of operating (20 or so triggers), the input of the monostable oscillator labeled “mono_trig”  (pin 2 of U1) would vary wildly, or was pulled to ground for extended periods of time. A zoom in of the problem area is shown below.

  Long story short I believe I was frying my monostable oscillator with an overvoltage on the trigger pin. Below is a capture of the circuit working, shortly before it died. Channel 1 is the input waveform, and channel 2 is the output of the pulse generator (mono_trig net). Notice there is a slight peak after the falling edge of the input, I’m suspicious my scope is missing the true peak here due to the BWL of my system. 
  

  My workaround circuit is shown below. The input signal is attenuated by -6dB (*0.5), then ac coupled to a new voltage at ½ VCC. Now the voltage at “mono_trig” should be ½ VCC ± ½ VCC, so there’s no need for the flyback diode.

  After these changes were made (see pcb below for the botch job) the circuit worked as intended. Channel 1 is the input signal, channel 2 is the output of the pulse generator, and channel 3 is the output of the monostable oscillator. Note the max voltage of channel 2 is well below 6V, and the 555 only triggers on the rising edge of the input signal as desired.

• Validation - Frequency Divider

  Jesse Farrell • 03/05/2022 at 19:54 • 0 comments

  This circuit worked as expected, but the changes mentioned in flip flop validation needed to be made. The schematic (mostly just hierarchical blocks) and pcb are shown below.

  The validation board worked up to ~32kHz after which the output pwm became distorted and missed pulses. Scope captures below with the maximum and typical operating frequency.

• Validation – 555 Flip Flop

  Jesse Farrell • 03/05/2022 at 19:32 • 0 comments

  This circuit induced several headaches… As a refresher the validation schematic and PCB are shown below. The circuit initially did not work; this was caused by an incorrect bjt footprint (flipped base– emitter pads). 

   After this change the flip flop worked but only for slower clock signals… This is because pin 2 of the 555’s in the latch circuits is essentially left floating when the BJTs are closed, creating an RC time constant of ~1ms. Basically, the trigger wasn’t resetting quickly enough. Reducing C23 and C24 to 10nF solved this issue, I could probably go lower still but for now this value seems consistent. I also reduced the base resistors to 5k which seemed to improve the reliability.

  The next issue was that the circuit was intermittently triggering on rising edges instead of falling edges. The scope capture below contains all the I/O of the first latch. Channel 1 is the clock input, Channel 2 is the data, Channel 3 is the latch output (note we expect this to be !data), and Channel 4 is the trigger. 

  To solve this, I tweaked the R17 – R15 voltage divider. Changing R15 to 7.5k pulls the voltage up by 400mV which then solved my issue. Note that this makes my system more susceptible to noise, since now I only have 600mV of +swing before the 555 is triggered. Below is the corrected circuit, same probe points as prior capture.

  Just as a summary the following changes were made for the eval board to work as expected.

  1. Fix npn footprint
  2. Change base resistors to ~5k
  3. Change voltage divider upper resistors to 7.5k
  4. Reduce capacitors C31/C32 to 10nF (perhaps a bit lower still)

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