PDP-8/Z16 - seamless extension from 12 to 16 bits?

Description

Thought experiment: if one would need to expand PDP-8 from 12 to 16 bits, how could that be done in least disruptive and simplest way? Could such as processor still execute 12-bit code?

Here is one possible solution:
- extend PC and A to 16 bits
- treat PC and "direct page" (0) as index registers, and add 6 more for a total of 8
- treat acc/link as one general purpose register pair, add 3 more for a total of 4
- introduce new addressing mode where destination address is calculated using true 2's complement offset
- I/O space remains at 64 locations
- memory space expands to 64k 16-bit words ("flat" addressing!)

Details

Some key parameters of the proposed extension design:

Internal registers extended from 12 to 16 bits
Programming model extended to contain:
- 4 accumulators (each with own L(ink) flip-flop)
- 8 index registers
1 of 4 accumulators and its Link are the present in classic PDP-8
2 of 8 index registers are present in classic PDP-8: PC (program counter) and zero page (it can be represented as index register with hard-coded value of 0)
Microcode driving the design is agnostic if CPU is running with basic or extended register set
Some of the index registers can possibly mimic HD-6120 "stack pointers" in future versions
Simple external circuit could force the CPU into "compatible" mode:
- If fetching instructions from lowest 4k of memory, force instruction upper 4 bits to 0
- If fetching data from lowest 4k of memory, extend bit 11 to 12..15 (seamless 2's complement representation)
"Compatible" mode will fail in following cases:
- 6-bit characters etc. swap "bytes" is now swapping 8-bit halves, not 6
- counting bits in word, assuming there are 12 not 16
- possibly bit-masks assuming 12 entries or similar
Needs verification, but most "simple" code should run with no or minimal modification in 16-bit mode too.

Instruction register is extended with 4 bits, 3 fields:

S (bit 15) - select register mode bit
- if 0, field R1:0 represents extension of MP bit in the instruction for a total of 3 bits:
  - 000 - zero page (X0 always contains 0)
  - 001 - PC
  - 010 - X2
  - ...
  - 111 - X7
- if 1, field R1:0 selects any of 4 accumulator/link pairs:
  - 00 - standard PDP-8 acc/link
  - 01 - acc/link 1
  - ...
  - 11 - acc/link 3
O (bit 14) - address offset mode

if 0, memory reference instructions calculate address by concatenating lowest 7 bits of IR with upper 9 bits of index register (same as usual PDP-8, so offset is 0 .. 127)
if 1, memory reference instructions calculate address by real 2's complement offset addition: index register value - 64 to index register value + 63

R1 (bit 13) - register select bit 1 (MSB)
R0 (bit 12) - register select bit 0

*IR15*	*IR14*	*IR13*	*IR12*	*IR11-9*	*IR11-9*	*IR11-9*
S	O	R1	R0	*000-101 (MEMORY REFERENCE)*	*110 (IOT)*	*111 (OP*R)
0	0	0	0	"compatible mode", just with 16-bit regs (00 - selects acc/link 0 and direct/PC reg)	compat mode	compat mode
0	0	X2	X1	6 additional index regs can be used, with 0..127 offsets	compat mode	compat mode
0	1	X2	X1	6 additional index regs can be used, with -64 .. +63 offsets	compat mode	compat mode
1	0	A1	A0	any of 4 acc/links can be used with direct or PC-rel addressing, offsets 0..127	I/O transfer on any acc/link	operation on any acc/link
1	1	A1	A0	any of 4 acc/links can be used with direct of PC-rel addressing, offsets -64..+63	I/O transfer on any acc/link	operation on any acc/link

Loading / saving index registers 0..7: using reserved IOT instruction (each index register having own IOT address), regardless of the IR bits 15..12 - note that this means mapping PC and direct (zero page) register into I/O space too for simplicity of implementation.

Loading / saving acc/links 0..3: with IR bits 1XXX any can be accessed in any instruction format. Given that there is still just 1 MQ register in the design, it can be used in OPR to communicate between accumulators.

Project Logs

Collapse

Internal CPU extensions

zpekic • 06/12/2022 at 02:31 • 0 comments

The schema below illustrates the additions to CPU programming model and how they are activated by the upper 4 bits of the instruction register. Some notes:

Microcode (or state machine) driving the instruction execution has no knowledge of the registers being used - it will use ACC/L or PC, or any X (index register) as the selection happens by pointing to 1 out of 4 or 1 out of 8 purely in hardware
ACC/L mux - based on IR15 (S), either ACC/L(0) will be selected, or any of 4 given by IR13:12
Once ACC/L is selected, rest of hardware (mostly ALU) sees 1 ACC/L exactly like in the legacy PDP-8
X mux - based on IR15 (S), selection is either 0:0:MP or X2:X1:MP - because direct page register is mapped to X0 and PC to X1, changing S bit on the fly from one instruction to another does not disrupt the program flow
X0 and X1 (zero, PC) are modified directly by microcode, so a bypass / force needs to be implemented on X mux but for simplicity is not shown below
X0 can be used at T (temporary) register - as long as during memory address calculation for memory reference instructions is set to 0. Typically, a microinstruction step would clear it to 0 before instruction execution phase
For memory reference instructions, first step is to evaluate the X + offset. IR14 (O) bit allows two ways to evaluate this - either "legacy" page|offset concatenation or real 2's complement addition. 2 muxs handle this - one taking X register value and the other the offset from IR

System "compatibility" schema

zpekic • 06/12/2022 at 02:16 • 0 comments

The picture illustrates a simple way to force a PDP-8/Z16 system into "compatible" mode. As this is a theoretical/or maybe FPGA implementation, system bus can be designed in non-multiplexed way, with DIN (data in) and DOUT (data out) buses separated.

Some notes about the schematic below:

DIN mux is supposed to feed instructions and data into CPU seamlessly if accessing "extended flat memory" (above 4k word), and if accessing PDP-8 basic 4k words, differentiate between instructions (force upper 4 bits to 0000 for "compatibility") and data (assume 2's complement so extent bit 11 to 12..15)
DOUT goes directly as 16 bit to I/O and memory
I/O can - based on actual device - be hooked up to any part of the 16-bit data bus, for example 8-bit devices could work on D7:0 or D15:8 etc.

Discussions

PDP-8/Z16 - seamless extension from 12 to 16 bits?

Description

Details

Project Logs

Collapse

Internal CPU extensions

System "compatibility" schema

Discussions

Similar Projects

16-bit CPU built in Logisim

The simplest 8-bit RISC CPU

OPC-1 CPU for CPLD

Kobold K2 - RISC TTL Computer

PDP-8/Z16 - seamless extension from 12 to 16 bits?

Become a Hackaday.io member

Just one more thing

Description

Details

Project Logs Collapse

Internal CPU extensions

System "compatibility" schema

Enjoy this project?

Discussions

Become a Hackaday.io Member

Similar Projects

16-bit CPU built in Logisim

The simplest 8-bit RISC CPU

OPC-1 CPU for CPLD

Kobold K2 - RISC TTL Computer

Does this project spark your interest?

Report project as inappropriate

Send message

Remove Member

Project Logs

Collapse