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Gitzian - A Flexible Display Decoder Ecosystem

"The display becomes a terminal. The computing happens elsewhere."

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This project is about building a flexible, modular display decoding platform that is not locked to a specific OS, hardware vendor, or panel type. Most devices today tightly couple hardware, software, and display into a single sealed system. That makes them hard to repair, hard to reuse, and quick to become obsolete. I wanted something different: a device I fully control — minimal, hackable, and adaptable. Your OS runs on a host machine you control. The decoder receives rendered frames and drives the display directly. This makes the system OS-agnostic — it works with any operating system capable of producing pixels.


What This Actually Is

This project is a modular display decoder. The idea is simple: the display becomes a terminal, and the computing happens elsewhere.

Instead of running an OS locally, the device receives rendered frames from a host machine and drives a display directly. The endpoint is not a computer. It is a deterministic hardware display pipeline.

The system is split into three independent layers:

Input — how frames arrive
Wi-Fi, LAN, serial, or custom links. The transport is abstracted so the display pipeline does not depend on a specific interface.

Decoder — core platform
An FPGA translates incoming frame data into panel timing and signaling. Display support is defined in firmware bitstreams rather than fixed hardware.

Output — display layer
Panels connect through small interface modules that handle voltage levels, backlight, touch lines, and panel-specific electrical requirements.

This separation means displays, interfaces, and host systems can all change independently.

Why This Exists

Because I have fun doing this and I want a communicator I can tinker with and can run a nice OS as well- Also most devices tightly couple compute + OS + display. That makes them hard to reuse, hard to repair, and obsolete as soon as software support disappears.

This project takes the opposite approach: the display endpoint stays minimal and stable, while performance scales on the host. Upgrading compute does not require replacing the device.

The focus is not building another handheld computer. The focus is building a reusable display endpoint that can be embedded into anything.

Current State

The architecture is implemented and running.

Frames are rendered on a host machine, encoded, transmitted, decoded in hardware, and scanned out directly to the panel. The endpoint does no high-level rendering and runs no desktop stack.

Measured full system consumption while actively streaming and driving a 720×720 panel at full brightness is ≤1.5 W total.

That includes decoding, display driving, and network operation.

Why Not Just Use VNC, RDP or X2GO?

Remote desktop stacks assume a full client system with a GPU, window manager, and large software footprint.

This platform is different:

  • hardware decode instead of software client

  • fixed pipeline timing instead of variable scheduling

  • minimal RAM and code footprint

  • deterministic scanout

  • predictable power usage

It is not a replacement for desktop remoting. It targets a different class of problem: ultra-low-power display endpoints.

What Makes It Different

The hardest part of custom hardware is always the display. Panels differ in signaling, timing, voltage, initialization, and documentation quality. Traditional designs lock support to one specific panel.

Here, one decoder platform can drive many displays. Supporting a new panel means adding a firmware configuration rather than redesigning hardware.

The goal is not one device. The goal is a reusable display ecosystem.


Roadmap Direction

Development is now focused on strengthening the platform rather than adding random features.

Current priorities:

  • expand verified display compatibility list

  • add GPU-accelerated encoder path (OpenGL-capable hosts)

  • refine PCB for reproducible assembly

  • package system into a clean demo device

  • design a simple hardware keyboard module

The existing software encoder already works reliably. Hardware acceleration is about efficiency headroom, not basic functionality.

Modular Design Philosophy

Everything is structured so parts can be swapped independently:

  • change display → update bitstream or swap bridge

  • change input link → swap module

  • change host → no device change required

The endpoint is intentionally simple so it stays stable while everything around it evolves.


Target Audience

This is for people who want control over their hardware:

  • embedded developers

  • FPGA users

  • system integrators

  • hardware hackers

  • anyone building custom devices with...

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  • Refined project and goals

    gitzi9 hours ago 0 comments

    The system is already running smoothly in real-time streaming conditions — and this is before any serious optimization work has even started.

    Right now the pipeline is still using early-stage encoder logic and unoptimized paths, yet frame delivery is stable, interaction is responsive, and overall behavior is already well within usable territory. This confirms that the architecture itself is sound and has plenty of performance headroom left once tuning begins.

    At this stage I’m not chasing speed yet. The focus is validating stability, timing behavior, and pipeline correctness first. Optimization comes later, once the baseline is fully characterized.

    Check out the video to see current performance as-is.

    I refined the goals and head over to a full device with battery and a case.

  • PCB Design completed

    gitzi02/11/2026 at 18:32 0 comments

    PCB designed for current roadmap.

    • Power consumption: Surprisingly low at full brightness ≤ 1.5W

    • Form factor: Board footprint significantly reduced vs previous revision

    • Architecture: Split into 3 modular parts for on-demand exchange

      • Input: Network module (e.g., WiFi or RJ45)

      • Processing: Decoder

      • Output: Display driver (supports different display types)

    Next steps:

    • Optimize network stream for full throughput

    • Perform latency testing

    • Implement touchscreen support

    • Publish results in the next few weeks

  • FPGA Decoder Milestone

    gitzi10/11/2025 at 09:20 0 comments

    Summary

    • Initial FPGA implementation complete for the decoder path.
    • Lattice STA and simulation confirm the pipeline meets the timing/perf budget for <20 ms/frame at 100 MHz.
    • This meets the near-term performance target on the roadmap.

    Next

    • Start PCB design for field testing (bring-up + measurements).

    Feedback welcome
    If you have any questions, recommendations, or general feedback, don’t hesitate.

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