• Design Choices

    Chris • 03/21/2026 at 23:32 • 0 comments

    The boards are due to be here within the week so now it's finally time to talk about some design decisions. In this case I'm talking about features, compromises, and room for improvement in future revisions, with no particular rhyme or reason.

    I/O

    First things first is the IO of the Crystal board. At least in my experience, the IO count of an FPGA is a really big deal. For the industries that use them, this makes sense. FPGAs are often used to do real time, true parallel processing by ingesting and fusing input from potentially dozens of sensors while controlling equally as many dozens of output pins. At my day job, we are looking to control about 150 IO in some of our most maximal applications. For context the Arduino Mega lists 54 digital IO. Say what you will, but the best way to get the most IO into an IC is to use a Ball Grid Array package. So considering that FPGAs are often demanded for high pin count applications its no wonder that the vast majority of FPGAs come in ball grid array package.


    This is starting to get long winded again. Long story short, I wanted an FPGA that was hand-solderable. There are some very nice Gowin FPGAs that are in QFN packages, amongst a few others. I ended up picking the Lattice Crosslink-NX in the QFN package because of its Radiant support. I also think its fun that there is only one ground pin on this bad boy - the center pad.

    This was almost a perfect choice for my purposes. The only major bummer is that only about half of the 40 IO on this bad boy is 3.3V compatible, while the read is "high performance" and only supports 1.8V. Most hobbyist electronics still use 3.3V logic and it doesn't seem like that trend is going anywhere soon. Not to say that it couldn't happen (see the switch from 5V logic to 3.3V over the past few years), but regardless, the Adafruit Feather specification requires 3.3V tolerant IO. Plus this is supposed to be user friendly. 

    Further, I wanted to have buttons, LEDs, and a PMOD connector. This means that I would far exceed the amount of 3.3V logic pins and would need to some level shifting of the 1.8V pins. Even then, I needed to do a lot of doubling up on functions. In retrospect, this isn't that big of a deal. Different MCU boards to that sort of thing all the time, I'm just used to being spoiled by the copious amounts of IO that an FPGA typically provides.

    You can see the two level shifters on the right side of the board connecting to pin 4-9, as well as handling the PMOD connector. I am a really big fan of this level shifter. It's bidirectional, high speed, works for up and down translation, and is 8 bits wide. Internally it's basically just a bank of logical level FETs packaged together but that's fine. 

    This honestly seemed to be a pretty good solution to my lack of 3.3V tolerant IO. I really would like to be able to drive a display using TMDS and an HDMI PMOD, so I am a little concerned that these devices will limit my clock speed too much. Using them in my current configuration, speeds of up to 100MHz signaling are supported but that depends on a lot of factors. 

    Analog to Digital Converters

    We've got them! All of the Nexus platform FPGAs have some pretty decent analog sampling circuitry built into them. There are two parallel ADCs that both can sample at 1 MSPS, which isn't too shabby. On a stock RP2040 the max sample rate is only 500 ksps without overclocking the ADC clock. There are some continuous time comparators as well. 

    Based on my IO constraints I was only able to break out 3 pins capable of taking analog samples because for every analog pin it would take up 2 digital IO and I just couldn't spare them. Also, I am using the internal reference, which isn't particularly accurate and limits the measurement voltage to around 1V, sort of an ESP8266 vibe. There is obviously room for improvement here, and sometime I want to take another look at in future revisions of the board.

     

    Buttons and LEDs

    ... Read more »

  • Motivation & Decent Alternatives

    Chris • 03/16/2026 at 00:49 • 0 comments

    Let me first admit at the time of writing this the boards have already been ordered, simply for the fact that I didn't want to lose my momentum on this project. All too often I have let perfection be the enemy of good and I am determined to try to break the cycle. For the same reason I intend to write this first project log in a stream-of-consciousness style that may feel rather messy. Nevertheless, writing something is better than nothing. Hopefully it's coherent and I get my points across.

    In this log I mainly want to talk about the motivation for this project, and talk about the current state of the FPGA hobbyist world from my perspective.

    Motivation

    Preface

    As I mentioned in the description, this project is meaningful to me on a personal level. Over the past few years I have had the opportunity to interact very closely with my local university and their FPGA design class. I work very closely with the professor at my day job as an FPGA engineer, so every year I get to chat with students, grade final projects, interview prospective interns. Just this past semester,  I even got to teach part of the course as an adjunct professor. 

    I really like FPGAs. I think about them almost constantly. I think they are just about the coolest electronic invention ever and its a joy that I get to work with them everyday. Not only that, I absolutely love teaching other people about FPGAs too. Just imagine: a magical IC that can basically take the form of any digital circuit, even a CPU! Of course, not everyone is interested, or even sees/understands the potential in the devices, which is fine. However, every semester there are a handful of students that "get it." It clicks for them just how powerful these devices can be and they understand why I get so excited about the subject. The problem is that after the class ends, these students are mostly abandoned. 


    Currently, in class use the Zybo Z7 board, and with one board rented out to a pair of lab partners. After the final project has been completed, the lab partners must then turn in their boards and get on with their well earned winter break. So this model not only encourages an unfair distribution of labor ("I will write the VHDL and you can do the report" often turns into, "I just did the whole lab by myself"), it also completely disqualifies the genuinely curious student from any tinkering or experimentation after the semester has ended. Not to mention using an FPGA in their upcoming senior design projects. It's really a bummer because every semester there is at least a handful of students who: 

    1. inquire about keeping their boards for longer, 
    2. want to buy the FPGA dev board for themselves
    3. ask for decent alternative FPGA boards

    Over the past few years of interacting with these students and the university here are the answer to the inquires above

    1. The department gives some strong discouragement for doing so. (Must be enrolled, doing research, they are expensive etc.)
    2. They are about 299 dollars at the time of writing. That's just not happening for a college student.
    3. There are no decent alternatives. Not really.

    It's this last point I want to focus on.

    No Decent Alternatives

    You might be telling yourself "surely there are plenty of good options out there."  You have probably even seen some decent attempts, and honestly, fair play. There have been plenty of decent attempts, but not for not for someone using who wants to use an FPGA on their own workbench or in their dorm room. Let's me highlight a few of my favorites, and address their short comings. 

    ICEBreaker

    Probably one of the most popular entry level FPGA dev boards and targeted specifically for students and workshops. Based on the ICE40 FPGA from Lattice, it's a strong contender, especially with the open source tool chain. At 80 dollars though, that might be worth a week or two of groceries for the frugal college student. Moreover, the form factor is bizarre...

    Read more »