CS09_CPU_ Schematic.pdf

PDF version of CS09_CPU schematics updated memory map 12/03/2026

Adobe Portable Document Format - 1.44 MB - 03/12/2026 at 11:28

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CS09-CPU-III-v2.kicad_pro.zip

JLCPCB production files for CS09_CPU_III_v2

x-zip-compressed - 1.49 MB - 03/13/2026 at 15:16

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RTCdriver.asm

Software interface DS1302 through 3 PIA lines. The code is provided ONLY for info in case someone would like to experiment. It is not very efficient and not the way the interface was finally done! Note that the code uses a couple of UniBUG routines to deal with user interface. These routines are exposed with a couple of 'jump' words at the start of UniBUG.

plain - 6.67 kB - 04/16/2026 at 09:42

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my_ds1302.v

This Verilog module provides the serial interface between CPU and DS1302.

v - 7.78 kB - 04/16/2026 at 09:38

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ibom.zip

Interactive Bill of Materials and board population overview (zipped) html file.

x-zip-compressed - 444.42 kB - 03/08/2026 at 15:15

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myIDEdrv_IRQ_suspend.asm

RBF IDE disk driver that uses the Suspend state whilst waiting for data to become available from disk. Once available burst DMA is used to transfer data to memory. This is the one that should be used. The other two are provided for info only.

plain - 7.97 kB - 04/09/2026 at 12:42

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myIDEdrv_IRQ.asm

RBF IDE disk driver sleeping while waiting for data ready from IDE releasing CPU

plain - 7.44 kB - 04/08/2026 at 09:39

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myIDEdrv.asm

RBF IDE disk driver w/o sleep hogging CPU during data ready waiting

plain - 6.08 kB - 04/08/2026 at 09:37

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myClock.asm

OS9 Clock module source code

plain - 4.47 kB - 04/02/2026 at 12:20

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myBoot_PIO.asm

Source code for Boot module, which resides together with OS9p1, in EPROM. This module loads the OS9boot file from disk.
Note that I have assumed the use of a 6309 CPU which has the TFM instruction for moving data fast. I should really change this to have optional compilation with a 6809/6309 flag ...

plain - 5.29 kB - 03/26/2026 at 11:15

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interleave.py

Code to convert .vhd virtual hard disk file from 256byte sectors to 512byte sectors ready for use with IDEdrv disk driver for OS9

x-python - 755.00 bytes - 03/24/2026 at 14:41

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crc24_new.py

Python command line programme to calculate OS9 CRC used to test the non-shift register approach that suits verilog implementation. Normally it is done in 6809 assembly which is relatively slow.

x-python-script - 2.29 kB - 03/13/2026 at 11:26

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3HP_3U_CS09CPU v9.step

Front plate for CPU board. Milled from 2 or 2.5mm Aluminium.

step - 1.10 MB - 03/08/2026 at 15:30

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