We are very happy to inform you that the Schematics Design of our new Powerboard Tyche Desktop is running fast thanks to the new Designer and to the NXP Devkit source design plus our Powerboard Tyche Notebook design. Designer took from the NXP Devkit design ( 2023 version) everything is related to the boot process and many parts from our Notebook design, except what is not needed for the Desktop version, like the Battery part.

You can check all the details regarding what we took from Devkit design and what we took from our Powerboard Tyche Notebook design.

At the end of July, we will provide the schematic design and the BOM to the factory, which will then begin the PCB design based on the schematics. Therefore, by the beginning of August (before the factory’s holiday closure), we will know the cost for the PCB design and prototype production. New donation campaigns will then start for PCB design and prototype production.

Today, July 14th, 2025, we’ve officially launched the donation campaign for the schematics. Before the end of July, we’ll make the down payment for the schematics design. We already have funds collected from the previous donation campaign for the CE certification (of the Powerboard Tyche Notebook), so we can advance money from that fund. However, it’s crucial to boost this new campaign and encourage everyone to donate so we can use fresh funds specifically for the schematics design.

SPECS

• Form Facttor: Micro ATX
• CPU: NXP T2080, e6500 64-bit Power Architecture with Altivec technology
  • 4 x e6500 dual-threaded cores, low-latency backside 2MB L2 cache, 16GFLOPS x core
• RAM: 2 x DDR3 Slots
• VIDEO
  • PCIE3 x16 VIDEO Card 1
  • PCIE2 x4 VIDEO Card 2
• AUDIO: C-Media 8828 sound chip, audio IN and audio OUT jacks
• USB: 3.0 and 2.0 ports
• STORAGE:
  • NVM Express (NVMe)
  • 2 x SATA2
  • 1 x SDHC card reader
• NETWORK:
  • 2 x Gigabit ethernet RJ-45 connecto

Yes, it’s possible to reach the goal to have a working Powerboard Tyche Desktop before the end of 2025, but is needed an extraordinary effort from donors because we depend on donations to cover all the steps that are coming : Schematics Design, PCB Design, Prototype Production and Tests.

Starting from today (July 14th 2025) you can make your donation, thanks!

Milestones

Phase 1: Actual Campaign Schematics Design : goal 30.07.2025

Phase 2: PCB Design : goal 30.09.2025 [depending on donations collected]

Phase 3: Prototypes Production: goal  30.10.2025 [depending on donations collected]

Phase 4: Prototypes Tests. : goal  30.11.2025 [depending on donations collected]

The milestone phases depend from your donation. Thanks!

We remain absolutely committed to making an Open-Hardware Notebook-based PowerPC machine a reality.

As we have already published on our past post we have changed the tactic, focusing on a desktop board first allows us to concentrate on getting the core computing platform stable and functional, tackling the complexities of a laptop form factor (like power management, screen integration, etc.) in a later stage if needed. This is a pragmatic step to ensure we achieve a tangible outcome by our 2025 target. What’s more the Powerboard Tyche Desktop version will be more cheaper than the Notebook version!

We value the experience of making our Open Hardware Powerboard Tyche based on PowerPC from scratch; this is possible thanks to the support of all donors and supporters, and the time and creativity of the activists who have been involved in this project over the years.

We ask you to share every-ware this call for support a strong flow of donations to cross the finish line of all donation campaigns to arrive by 2025 with produced, tested and functioning prototypes!

TO DONATE

Hello everyone, we know it’s been quite some time since our last update on November 21, 2024.

We really appreciate your patience! Despite the silence on our end, we’ve seen that our incredible community – both old friends and new supporters – have continued to donate continuously. An infinite thanks to all of you, our amazing current, past, and future donors! Your unwavering support truly fuels our efforts and keeps the dream alive.

Short story

As we shared in our last post, the work with the previous designer hit a significant hurdle: we just couldn’t get the board to reach the crucial boot stage.

This led us on a search for a new designer, someone with specific skills and experience with PowerPC architecture. We were really pleased to find a talented new designer who was available from the beginning of 2025, who can even rely on an additional person who is an expert in firmware programming. Following our plan, we used January and February to make the big move, getting all the equipment transferred over to this new designer’s team.

We held off on publishing updates because, honestly, we were waiting for that breakthrough moment – the good news we could finally share with all of you. As things were showing quite promising (e.g. improved CPU signals outputs), we had high hopes that this new collaboration would quickly move us past the booting issues. In parallel, we also tried improving U-Boot and led an additional T2080RDB, the development board that was kindly provided by NXP, to one of our collaborators, but due to personal health problems, he can no longer contribute to the project.

Our work with the new designer has been focused on rigorous testing. On April 9th, we saw that the board’s behavior was frustratingly similar to the devkit – it still wasn’t booting. This prompted a dedicated session on April 14th for one last intensive attempt to find the root cause. As part of this deep dive, we de-soldered the Marvell chip, which is the SATA3 controller.

Removing this component was actually something we had already planned to do for the upcoming prototype version as we streamline the design. To help isolate the issue even further, we also de-soldered the Pericom chip.

The overall outcome? Despite taking these significant steps, the board still did not boot. It exhibited exactly the same behavior. We were, frankly, quite upset and left without words.

It’s incredibly challenging when you put in the effort, try to simplify things, and the core problem persists. So far, we have spent around 6000 Euros with the newly hired hardware designer, and even if things have improved, showing the expected NXP documented behaviors of the NXP reference development board, after two years with the prototype motherboards in our hands, we still are not able to boot it.

So what’s next?

This difficult moment, however, has reinforced our resolve and led to a strategic adjustment, as the title suggests. We remain absolutely committed to making an Open-Hardware Notebook-based PowerPC machine a reality.

By the end of 2025, we are determined to do whatever it takes to have at least a stripped-down functional desktop version of our Powerboard Tyche up and running.

We change tactics

Focusing on a desktop board first allows us to concentrate on getting the core computing platform stable and functional, tackling the complexities of a laptop form factor (like power management, screen integration, etc.) in a later stage if needed. We even plan to revert to the NXP original CPLD used in their development board, not the version we previously selected for the notebook prototypes. This is a pragmatic step to ensure we achieve a tangible outcome by our 2025 target.

The path forward still has its challenges. We need to understand precisely why the notebook prototype board isn’t booting and what electronic redesign might be required, and for this, we are in contact with experts directly at NXP....

The hardware designer who created our Powerboard Tyche worked between April and July on one of the three prototypes, focusing on fixing the board firmware. These fixes required a series of checks to determine if any additional adjustments were needed for the board itself, and a complete analysis of electronic signals was performed. This analysis was provided later in September. The same fixes were applied to the second prototype (we have three prototypes).

u-boot 2018.11 enabled AMD video cards

Additionally, Max Tretene from ACube Systems was hard at work on our NXP T2080-based DevKit and completed a newer version of U-Boot in May, which finally enabled graphical output on AMD Radeon video cards during booting. You can find the updated source code on our GitLab. Below you can see the new U-Boot in action booting up the NXP T2080-based DevKit.

Below is a photo showing the Powerboard Tyche during an electronic test session conducted last August.

In August, the hardware designer sent back two prototypes to our firmware engineer. ACube Systems purchased an oscilloscope to continue analyzing signals on the prototypes, since the oscilloscope previously used by the firmware engineer was on loan.

In September, signal analysis using the oscilloscopes began, comparing the NXP T2080-based DevKit and our Powerboard Tyche to identify differences. Many differences were found in the power-up sequences, so we asked the hardware designer to fix the CPLD program responsible for governing the signals.

Below is a picture of the expected power-up signals as explained in the T2080 Manual.

Below is picture showing the signals from the Powerboard Tyche last August, a picture extracted from the Test Report provided by the hardware designer.

As you can see above there is some difference of PORESET_B and HRESET_B between what was found during the hardware tests on pur board and what is expected in the NXP manuals.

In September, a new series of tests were performed. Below are two pictures from the oscilloscope showing the output of different attempts while reprogramming the CPLD of the Powerboard Tyche.

As we can see on the screenshot even the tension of 2,51 volt was wrong, as it should be not more than 2 volt.

During September and October, there were many reprogramming cycles of the CPLD. Each time, the hardware designer recompiled the HDL of our CPLD and sent it to our firmware engineer, who had two prototypes in hand. Reprogramming the prototypes was quite slow, as neither the hardware designer nor the firmware engineer were working full-time in our project. We sent one prototype back to the hardware designer, and by the end of October, he had completed the CPLD updates. At the end of this hard work the CPLD finally generates the expected power-up signals, reproducing the same signals generated during power-up of the NXP T2080-based DevKit.

The final version of the CPLD firmware (published on GitLab) modifies the behavior of the two signals PORESET (yellow) and HRESET. Indeed, the oscilloscope shows that the two signals now behave differently compared to previous versions.

By the end of October, the signals on the Powerboard Tyche finally looked correct (picture below)

As you can see the now the tension is correct, around 1,95v, in August was 2,51v

Unfortunately, the changes to the CPLD did not resolve the boot-up process of the entire board.

Strangely enough, during tests we found differences in the power-up behavior between two of the prototype boards: one in the hands of the firmware engineer (FE) and the other in the hands of the hardware designer (HE). Here are the three differences we found:

• On the HE board, the ASLEEP LED stays off if the SD card with U-Boot is inserted and lights up if it is not inserted.
• On the FE board, the ASLEEP LED always stays on, regardless of whether an SD card is inserted or not.
• On the HE board, the oscilloscope shows activity...

it’s a quite some time has passed since the beginning of July when we posted about the start-up ramp that carefully calibrated, programming a complex integrated circuit with some logic (i.e. ramps, voltage thresholds, internal ways of making the PWM regulator work, and so on) and when the Complex Programmable Logic Device (CPLD) (Lattice LCMXO640C-3TN100C FPGA) was programmed for the very first time in order to manage all external peripherals connected to it.

In July we figured out  that a Jtag Debugger was very needed to debug our Powerboard Tyche, the only way to solve the causes of not seeing any U-Boot output. We were able to buy such a debugger thanks to the donations we are collecting with the  current campaign, we thank all donors for their support.

The debugger is  the NXP CWH-CTP-BASE-HE Jtag Debugger + NXP CWH-CTP-COP-YE “Probe Tip, Removable, For Power Architecture Processors, JTAG to CodeWarrior TAP Base Unit” and, together with one of the three prototypes, we shipped it in August to Max Tretene that kindly accepted to be directly involved in the debug process of the motherboard. Soon, the task proved to be quite challenging, so after an internal discussion, we decided to  offer Max a reimbursement for all the time he was spending on the job, a reimbursement that was made possible to the donations we are receiving with the current campaign.

Dealing with hardware debugging is quite a hard and tedious job, and it was not easy to see something useful on the Jtag Debugger connected to the prototype motherboard. An additional adapter was required to attach the debugger because of the difference in the pin dimensions (2 vs 2.5). Max found it quite useful using the jtag debugger with our NXP T2080-RDB Devkit that was also shipped to him, because it allowed to test the procedure on a working platform and helped understanding the right configurations of the switches to boot up the board.

As our PowerBoard Tyche have not the third switch like the NXP T2080-RDB Devkit a few additional resistors were required to setup correctly the board to be able to switch on the Code Warrior debug connected to our Powerboard Tyche. Not just that, an additional update to the CPLD chip was required to setup the debugging system correctly. Finally, on the 16 of October, Max was able to see some sign of life from the NXP T2080 CPU on SRAM and on NAND Memory, as you can see in the screenshots below. These days we are working on NOR programming, waiting in the meantime for a CPLD update from the hardware designer. The NOR programming is needed to have access to the DDR and then start U-Boot.

Some possible changes to the hardware design

All these hardware tests were useful for planning some changes to the hardware design: few missing resistors for enabling the u-boot switches must be added and we need to move one chip because it does not fit quite right in the eclipse chassis.

The recent worldwide electronic components shortages we faced when making  the prototype Powerboard Tyche boards caused an unexpected -and incredible-  increase of the prices. More recently chip prices seem to be coming back to more reasonable prices, with the exception of the Marvell Sata3 controller.

As a consequence, we are evaluating the removal of the Marvell Sata3 controller to both free very-much needed space space and save some costs because at the moment such a chip costs around 90 euros per piece, quite a lot.

In fact, nowadays most SSD are available at a very good price with the M.2 form factor, so a Sata3 connection is not that essential anymore. People in a desperate need for a Sata connection could use the two Sata2 controllers inside the T2080 CPU.

Below we list the availability and prices...

Once again we want to thank you all for the great support and great enthusiasm you demonstrated during the CE mark donation campaign. We ended the campaign with a total amount of 12500€ (https://en.wikipedia.org/wiki/CE_marking), this is a huge milestone for us all and we are so very grateful.

By financing the CE mark certification you have shown us that you believe in the project and our vision of creating a fully open hardware notebook motherboard based on the alternative PowerPC CPU architecture.

We closed the campaign with around € 4000 more than expected, and this extra money will cover some of the extra and unplanned costs we faced for the increased price of electronic components and the extra costs of the three MXM video cards (360 USD each).

The CE mark certification is a mandatory requirement for selling electronic products in the European Union. It ensures that our notebook motherboard meets the safety, health and environmental standards of the EU. Without it, ACube Systems would not be able to launch and sell our Notebook on the EU market. Getting the CE mark certification is not an easy nor a cheap process as it involves rigorous testing, documentation and quality controls.

However, the CE certification process can be performed only when the product can be considered completely finished, and that means once the board works, the cooling metal pipes are in place and all is assembled into the selected slimbook eclipse chassis.

Current activities

The Tyche Motherboard has surpassed all the electrical checks, and now the the key activities being performed concentrate on the hardware initialization procedures.

The start-up ramp was carefully calibrated, programming a complex integrated circuit with some logic (i.e. ramps, voltage thresholds, internal ways of making the PWM regulator work, and so on).

The Complex Programmable Logic Device (CPLD) is a Lattice LCMXO640C-3TN100C FPGA is programmed to manage all external peripherals connected to it (see the block diagram and wiring diagram on page 15), manage the interrupts, data, boot reads, set resources according to the CPU and is able to reset all peripherals.

Working on U-Boot

Currently, a small team of volunteers are working on U-Boot . We are decided to buy a JTAG debugger, a quite useful tool indeed that will make the hardware debugging much easier.

We learnt how to configure and build U-Boot, and we set up a cross-development PowerPC toolchain and the related Device Tree Blob that is used to describe the physical configuration of each hardware component available on the motherboard. You may keep an eye on our attempts by looking at our GitLab pages. We started by re-compiling our old U-Boot binary dating back to 2019, the one that we are currently using on our NXP T2080RDB devkit and also trying to compile a newer U-Boot version from a the DENX mainline vanilla branch without our patches. We are now kindly assisted by Max Tretene, the same guy working at ACube Systems that compiles U-Boot for their motherboards such as the Sam440 or the Sam460ex. Max is currently available to introduce hardware support to AMD/ATI Radeon graphics cards in U-Boot, (ndr.: he recently told us that his spare times is not enough so we are proposing him to work under payment) stay tuned for more in-depth posts about it. In the hope of speeding up the development, we provided Max Tretene with our NXP T2080RDB devkit in early June.

We want to thank the dedicated small group of volunteers and especially Max Tretene for their precious spare time spent in trying to configure and compile U-Boot, we very much appreciate their availability and effort, even if a successful result is yet to comes. In addition, we greatly appreciated the offer made by a professional engineer – not to be disclosed yet- that is ready to work for us on U-Boot for a very reasonable amount of money.

Launch of a new fundraising campaign

After quite some internal discussion, we finally...

The laptop prototypes testing is progressing great. We tested the primary power supply stage of the CPU, one the most power hungry components in the board, and it is being fine-tuned thanks to a programming apparatus. The chip in charge to power up the CPU NXP T2080 is the Texas Instruments TPS544B20RVFT (Switching Voltage Regulators 4.5-18V 20A SWIFT) as explained at page 37 in our electrical schematics.

The start-up ramp needs to be carefully calibrated, a complex integrated circuit with a some logic that needs to be programmed to make it work properly (i.e. ramps, voltage thresholds, internal ways of making the PWM regulator work, and so on).

The other power supplies are a half a dozen voltage regulators and are meant to power elements such as the PCIe, the RAM, the internal peripheral buses, the connected devices, the Non-Volatile Memory Express (NVMe) and the clock generators the are essential to make the board work properly. The Eclipse Legacy Battery was tested and is recharging properly.

The Complex Programmable Logic Device (CPLD) is a Lattice LCMXO640C-3TN100C FPGA and has to be programmed to manage all those external peripherals connected to it (see the block diagram and wiring diagram on page 15 ), manage interrupts, data, boot reads, set resources according to the CPU and reset all peripherals.

So far so good, the electronic design seems to work correctly, at the moment we are only fine-tuning each electronic component. If all checks continues like this, we might end all electronic debugging in the next few weeks and we can consider this very delicate phase successfully completed. After that, we plan to place the first code in the CPLD, and right after that we should be ready to load U-Boot, the first-stage and second-stage bootloader. We are trying to re-patch a recent version of U-Boot, quite some time has passed since we patched it to make it recognizing the graphic board we mounted on the PCIe port on the NXP T2080RDB board. Not just that, we must carefully customize the device tree to correctly map all peripherals available on the motherboard.

If for it concern the electronical components we can safely rely on the (paid) support of an expert engineer, for setting up U-Boot it’s up to us to make it work properly, and more importantly, to make it correctly recognize all peripherals, especially the SD card, the FLASH and, even more importantly, the two DDR3L RAM slots.

Donations and professional for u-boot

In addition, after an initial round of experiments, we are still struggling to successfully customize U-Boot and to properly setup the device tree. Most of us already spent quite some time on the task during our spare time (remember, we are all volunteers with a proper day job and a personal life ;), so we are seriously evaluating to assign the job to a professional to get the job done in a reasonable amount of time, and to do that we need your financial support!

Published Powerboard Tyche PCB reworked source

Finally, the reworked PCB design source of Powerboard Tyche with the updated available components is ready ( in older posts you can go more deep about “our” electronic components shortage issues). This work was made using Mentor Expedition and it is ready and uploaded into our repository with all reported issues fixed, including issue number 5, the last one corrected . Thanks to our collaborators we are able to export this work using Altium form so the next days we will publish it and we will try to convert it to Open Source Kicad format ( and probably loosing something in the conversion process) . In our older post we have give more details regarding the PCB sources.

Inside Output folder you can find many interesting files easy simple viewable like the “the plot separate sheet” CAM350/DFMSTREAM and the Motherboard Assembly TOP and BUTTOM.

As a conclusion now we have everything to produce and make the hardware tests in September.

In July we have published more details about the rework design due to the global shortage of electronic components

Rework of a part of the mobo and situation of the components

As you know, we were having troubles to find a few components in the marked (listed below) not only because of their availability but also due to the increased price. After an extensive research, the designer was able to identify the replacement components.

Below, a detailed list of unavailable or extremly expensive parts that the designer is replacing with other readily-available components:

• 1 per pcb Transistor: NPN; BSR17A bipolar; 40V; 0.2A; 0.35W; SOT23 – ON SEMICONDUCTOR > 3100>#/strong### cost increase from 0,5 euro to 16,50 euro per piece
• 4 per pcb Field Effect Transistor –NDC7002N MOSFET 2N-CH 50V 0.51A SSOT6 – ON SEMICONDUCTOR : >1100>#/strong### cost increase from 0,50 euro to 6,5 euro per piece
• 2 per pcb MOSFET N-CH 100V 60A PPAK SO-8 SiR870DP – Vishay Siliconix > 3250>#/strong### cost increase from 1,53 euro to 50 Euro per piece
• 1 per pcb Parallel NOR Flash Automotive Memory MT28EW01GABA1HJS-0AAT – MICRON > 3250% cost increase from 13 euro to 423 euro!!!
• 1 per pcb IC EEPROM 256KBIT I2C 1MHZ 8SOIC AT24C256C-SSHL-B – Microchip Technology > 1000>#/strong### cost increase from 0,29 euro to 2,5 euro
• 1 per pcb 24-bit translating 1.65- to 5.5-V I2C/SMBus I/O expander TCA6424ARGJR – Texas Instruments Not Available
• 1 per pcb 24 MHz XO (Standard) LVCMOS Oscillator ASFLMB-24.000MHZ-LC-T – Abracon LLC – Not Available
• 1 per pcb I/O Controller Interface IC HI-PERFORM LW PWR SM FOOT USB 2.0 HUB USB2514-AEZC – Not Available
• 1 per pcb Two-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I/O Controller 88SE9235 – MARVELL – 980 euro!!!!!!!
• 1 per pcb 6-port, 12-lane, PCIe 2.0 Packet Switch PI7C9X2G612GP – Diodes – 700 euro!!!!
• 1 per pcb Power Switch ICs FDC6331L – onsemi / Fairchild – >3300>#/strong### cost increase from 1,25 to 41,6 euro
• 1 per pcb Switching Voltage Regulators 4.5-18V 20A SWIFT TPS544B20RVFT – Texas Instruments – 90 Euro!!!
• 6 per pcb Switching Voltage Regulators 4.5-V to 28-V, 6-A TPS56637RPAR – Texas Instruments – > 10000>#/strong### cost increase from 3 euro to 344 euro per piece ( 6 piece = 2.064 euro!!!)