BeagleLogic Standalone

Excited to announce that I have released BeagleLogic boards to OSH Park for manufacturing, and also ordered parts for the initial prototypes of BeagleLogic.

The shared project for BeagleLogic can be found here: https://oshpark.com/shared_projects/3JUihv0l

Here's a screen render of the final board:

Here's how the board looks, courtesy KiCAD's 3D renderer:

It measures 10cmx6cm in size. I was able to pack everything in 4 layers.

The board goes out for fabrication on Monday.

Here a screenshot of the routing in progress:

I might have to use 6 layers instead of the original 4 to fully fit everything. I expect the routing to be complete by this week-end after which I will release the design to manufacturing.

One of the bottlenecks when using BeagleLogic in conjunction with a PC is that unless you are using the web interface, the logic capture needs to happen on the BeagleBone (in an SSH shell) and then the captured file needs to be copied to the PC in order to view the capture using the PulseView software in the sigrok suite and do further post-processing.

To merge these two steps into one, I am building a TCP server for BeagleLogic that will run on port 5555 of the BeagleLogic standalone. PulseView supports connecting to Logic Analyzers over the TCP/IP protocol, and hence I am building support for the BeagleLogic TCP protocol into libsigrok so that it can natively interact with BeagleLogic standalone, and support capturing logic data directly from the PC, skipping the intermediate step of copying the files from the BeagleLogic standalone onto the PC.

The TCP server is built using NodeJS and is currently checked into the BeagleLogic repository. It can be found at - https://github.com/abhishek-kakkar/BeagleLogic/blob/master/tcp-server-node/server.js

Now to make the TCP server work with PulseView and retrieve captures directly into it.

I am migrating the original content hosted at the BeagleLogic wiki over to a new hosted documentation at ReadTheDocs.io. Please check it out at:

https://beaglelogic.readthedocs.io/

Suggestions and Feedback welcome.

View the article here:

http://hackaday.com/2017/07/19/hackaday-prize-entry-beaglelogic/

Thanks to @Brian Benchoff for the Hackaday Prize entry feature blog article.

Announcing the release of a new System Image for BeagleLogic, which is now available here

This release is based on Debian 9 (Stretch), which is the newest stable version of Debian GNU/Linux available.

NodeJS in this system image is upgraded to the latest available v6.11 LTS release (it is used by the web interface)

Also the sigrok components bundled in this image have been upgraded to the libsigrok 0.5.0 release which happened in June 2017. They incorporate new features and protocol decoding is expected to be faster as a result of the new protocol decoder API.

The device tree overlay in BeagleLogic is now loaded using uboot cape overlay support which requires that one hold down the switch to boot from SD card by default. Alternatively one can also update the bootloader on the eMMC so that it can support uboot overlays.

Login as root is by default disabled in the new system images for better security. Therefore the BeagleLogic image now allows attributes (samplerate, sample unit, ...) to be set through the default user without requiring root permissions. This also improves the quality of experience.

It is highly recommended that users update to the new system image.

Today I completed the schematic.

The completed schematic and design is online at https://github.com/abhishek-kakkar/beaglelogic-standalone.

Apart from 16 logic inputs, BeagleLogic standalone shall also incorporate a 24-pin expansion header that breaks out:

• 1 UART
• 1 I2C
• 1 SPI
• 1 Quadrature Encoder input (2 pins)
• 2 PWM outputs
• 6 GPIOs
• CLK input to PRU1 is also broken out for experimental synchronous captures with BeagleLogic

Work on the layout will begin soon.

Here's a link to the PDF of the schematic.

BeagleLogic Standalone schematic capture is now 80% completed. The following components/features have been placed:

• Logic Analyzer frontend
• OSD3358 supporting circuit
• Gigabit PHY (Microchip KSZ9031) and Ethernet Port
• USB Ports
• SPI Flash
• SD Card slot and eMMC
• RTC

The following components are to be placed:

• Expansion header containing UART, SPI, I2C and PWM ports
• Serial Debug Connector
• Some additional GPIOs

You can view the partially completed schematic at this link.

When the kernel for BeagleLogic was initially written in 2014, it was based on the 3.8.13 kernel that featured first-class support for device tree overlays and BeagleBone capes.

The cape manager disappeared in later kernel versions, only to reappear in kernel version 4.0 and above. However the API for controlling the PRUs had changed too much and it made BeagleLogic incompatible with those kernel versions. Thus BeagleLogic had to stick to the 3.8.13 kernel version, even though nicer things were happening in future kernel versions.

The API for the PRUs became stable enough starting with kernel version 4.4 (there were official TI examples) so that I could look at porting BeagleLogic to this version. Ultimately, by end of May I sat down and rewrote parts of the PRU firmware (GitHub link to commit history) and by mid-June the kernel module was ready. I was advised to use the 4.9 kernel instead of 4.4 I was originally planning to port it to, and as a result it is up-to-date with the latest TI kernel as of now. It's already submitted to and included in the BeagleBoard's kernel repository (4.9 branch).

I hope that keeping it in sync with upcoming kernel releases will be easier and something I will actively do for BeagleLogic.