Yann Guidon / YGDES
YGREC8_20231214.tbzVHDL assembler worksx-bzip-compressed-tar - 205.14 kB - 12/14/2023 at 05:52 |
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YGREC8_20231012.tbzThe new wave of manuals. No source code yet.x-bzip-compressed-tar - 141.32 kB - 10/12/2023 at 05:52 |
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YGREC8_VHDL.20211120-2.tgzx-compressed-tar - 372.71 kB - 11/20/2021 at 14:46 |
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YGREC8_VHDL.20211120.tgzx-compressed-tar - 372.09 kB - 11/20/2021 at 08:56 |
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YGREC8_VHDL.20211118.tgzassembler refactored, supports DW and re-assemblyx-compressed-tar - 360.31 kB - 11/18/2021 at 17:29 |
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YGREC8_VHDL.20211114.tgzALU8 still bork and assembler is incompletex-compressed-tar - 359.56 kB - 11/14/2021 at 08:08 |
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YGREC8_VHDL.20211112.tgza better assembler starts to work.x-compressed-tar - 358.68 kB - 11/12/2021 at 06:18 |
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dictionary.vhdla dynamic lookup table for the assembler's symbolsx-vhdl - 5.47 kB - 11/08/2021 at 11:21 |
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YGREC8_VHDL.20200825.tgzsome syntax highlighting, new SR FF macrosx-compressed-tar - 351.15 kB - 08/25/2020 at 04:42 |
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YGREC8_VHDL.20200821.tgzTAP's Selector unit OKx-compressed-tar - 349.16 kB - 08/22/2020 at 00:52 |
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YGREC8_VHDL.20200815.tgzTAP bit scrambling order is working againapplication/x-compressed-tar - 301.32 kB - 08/16/2020 at 01:53 |
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YGREC8_VHDL.20200814.tgzBack to Gray6s...x-compressed-tar - 297.88 kB - 08/15/2020 at 04:45 |
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YGREC8_VHDL.20200813.tgzGray7 OK !x-compressed-tar - 278.49 kB - 08/13/2020 at 03:24 |
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YGREC8_VHDL.20200812.tgzMUX64 & Gray7s behav.x-compressed-tar - 278.29 kB - 08/12/2020 at 15:24 |
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YGREC8_VHDL.20200811.tgzTAP reboot, "SYNTHESIS OK" on some filesx-compressed-tar - 259.30 kB - 08/11/2020 at 06:26 |
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YGREC8_VHDL.20200801.tgzTAP/Slice in the works...x-compressed-tar - 358.84 kB - 08/02/2020 at 02:00 |
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YGREC8_VHDL.20200730.tgzInstruction debug slice added.x-compressed-tar - 334.00 kB - 07/30/2020 at 21:30 |
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YGREC8_VHDL.20200728.tgzThe selector works. TAP's core is almost done :-)x-compressed-tar - 320.59 kB - 07/28/2020 at 01:57 |
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YGREC8_VHDL.20200727.tgzTAP/Counter added (and lib fixed)x-compressed-tar - 318.65 kB - 07/27/2020 at 06:07 |
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YGREC8_VHDL.20200723.tgzGreat progress on TAP (MUX64 / BBT-BC and Gray counter done)x-compressed-tar - 263.17 kB - 07/22/2020 at 23:34 |
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YGREC8_VHDL.20200718.tgza few things work, TAP and ALU are in development...x-compressed-tar - 241.87 kB - 07/18/2020 at 04:53 |
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INC8_ASIC_test.cjsINC8 (version ASIC) with some test featurescjs - 5.08 kB - 07/15/2020 at 18:49 |
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CLA8_NAND.cjsCircuitJS source code for the NANDified Carry Lookaheadcjs - 7.64 kB - 03/17/2020 at 00:05 |
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Add8.cjssource code of the CLA8 for falstad.com/circuitcjs - 8.16 kB - 03/05/2020 at 23:24 |
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YGREC8_VHDL.20200119.tgzAdded FSMALU_2020 is bork, needs debug x-compressed-tar - 143.02 kB - 01/19/2020 at 04:14 |
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YGREC8_VHDL.20200105.tgzx-compressed-tar - 138.15 kB - 01/05/2020 at 05:34 |
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YGREC8_VHDL.20191231.tgzLast release of 2019, new start for 2020 with the new, ASIC-friendly, ROP2 unitx-compressed-tar - 119.74 kB - 12/31/2019 at 02:05 |
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FrontPanel_coords_4.diax-dia-diagram - 7.42 kB - 09/29/2019 at 05:07 |
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FrontPanel_coords_4_seri.diax-dia-diagram - 4.74 kB - 09/29/2019 at 05:07 |
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YGREC8_VHDL.20190422.3.tgzR7 decoder in A3P tilesx-compressed-tar - 174.65 kB - 04/22/2019 at 01:39 |
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YGREC8_VHDL.20190422.tgza better decoder for the register setx-compressed-tar - 173.01 kB - 04/21/2019 at 17:58 |
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YGREC8_VHDL.20190421.tgzRedesigning the register setx-compressed-tar - 155.92 kB - 04/21/2019 at 00:13 |
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YGREC8_VHDL.20190412.tgzNew gates library, better ALU and decoderx-compressed-tar - 152.59 kB - 04/11/2019 at 23:23 |
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YGREC8_VHDL.20190404.tgzmore versions of the ALU8 decoderx-compressed-tar - 148.85 kB - 04/04/2019 at 23:10 |
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YGREC8_VHDL.20190401.tgzspun off the decoder logic for deglitchingx-compressed-tar - 144.44 kB - 04/01/2019 at 02:57 |
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YGREC8_VHDL.20190328.tgzALU implemented as 3-input logic gatesx-compressed-tar - 143.44 kB - 03/28/2019 at 20:20 |
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YGREC8_VHDL.20190325.tgzALU redesignedx-compressed-tar - 109.39 kB - 03/25/2019 at 05:22 |
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YGREC8_OpcodeMap_v2.svgAND and XOR swapped for the new ALU designsvg+xml - 24.80 kB - 03/23/2019 at 01:09 |
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YGREC8_VHDL.20190317.tgznew assembler/disassembler in VHDLx-compressed-tar - 101.43 kB - 03/17/2019 at 02:53 |
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YGREC8_InstructionFormat_v7.svgsvg+xml - 11.40 kB - 01/13/2019 at 23:30 |
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YGREC8_OpcodeMap_v1.svgsvg+xml - 24.80 kB - 01/13/2019 at 22:24 |
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YGREC8_VHDL.20190101.tgzassembly passes self-testsx-compressed-tar - 114.55 kB - 01/01/2019 at 15:25 |
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YGREC8_VHDL.20181230.tgzassembler reboot, not finished but promising !x-compressed-tar - 113.57 kB - 12/30/2018 at 07:05 |
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YGREC8_VHDL.20181101.zipAdded the proasic3 VHDL library for rough gate-level simulations, many incoherent or obsolete files though.Zip Archive - 109.48 kB - 11/01/2018 at 16:04 |
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YGREC8_InstructionFormat_v5.svgV5 with Imm4 fieldsvg+xml - 10.89 kB - 11/01/2018 at 15:59 |
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YGREC8_VHDL.20181017.tgzAdded the ProASIC3 "tiles" libraryx-compressed-tar - 60.71 kB - 10/17/2018 at 04:14 |
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ygrec8_20180116_yg.svgCore diagram in SVG, added LDCx MUXessvg+xml - 17.96 kB - 01/17/2018 at 17:38 |
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YGREC8_InstructionFormat_v3.svgImm9 removedsvg+xml - 6.99 kB - 01/12/2018 at 18:57 |
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YGREC8_VHDL.20171209.tgzAdded: license, readme, mustfail...x-compressed-tar - 36.61 kB - 12/08/2017 at 23:21 |
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ygrec8.nanorcColoration syntaxique pour l'éditeur de texte Nanonanorc - 1.16 kB - 12/08/2017 at 14:43 |
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ygrec_debug.svgHow the YGREC8 is split and controlled for debug, development and testsvg+xml - 8.55 kB - 12/03/2017 at 16:26 |
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ygrec8_20171122_yg.svgcore diagram in SVGsvg+xml - 16.46 kB - 12/03/2017 at 16:26 |
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YGREC8_InstructionFormat_v2.svgInstruction format diagram in SVGsvg+xml - 7.50 kB - 12/03/2017 at 16:16 |
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YGREC8_VHDL.20171117.tgzStarting to code the assembler.x-compressed-tar - 19.08 kB - 11/17/2017 at 09:51 |
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YGREC8_VHDL.20171116.tgzExecutes its first instructions, and other enahncementsx-compressed-tar - 16.41 kB - 11/16/2017 at 05:28 |
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YGREC8_VHDL.20171114.tgzAdded some BRAM blocks and ... a core ! (it compiles but need to be tested now)x-compressed-tar - 14.65 kB - 11/14/2017 at 06:41 |
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YGREC8_VHDL.20171113.tgzmuch better integration now.x-compressed-tar - 9.38 kB - 11/13/2017 at 02:19 |
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YGREC8_VHDL.20171112.tgzALU, SHL, REG, INC8, INC16...x-compressed-tar - 7.53 kB - 11/12/2017 at 05:22 |
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YGREC8_VHDL.20171111.tgzALU, SHL and REG units, with their testbenches and 2 versions each, targeted for A3P FPGA.x-compressed-tar - 5.69 kB - 11/11/2017 at 14:49 |
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ALU8.tgz2 versions of the ALU, one testbench and one script to run it all with GHDL.application/x-compressed-tar - 2.33 kB - 11/10/2017 at 07:06 |
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YGREC8
A byte-wide stripped-down version of the YGREC16 architecture