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• Quick update

  Hacker404 • 04/24/2016 at 05:15 • 0 comments

  Well my old computer died and i lost a lot of work. I am using a laptop now and it's only got 2 cores (the desktop had 4).

  So I am starting over a bit now. I switched to wire wrap because I have a similar project and I can use the same development bits to start with.

  So here's the board -

  And here is where I am up to with re-writing the VHDL -

  It's 50 x 37.5 character boxes of 8 x 8 pixels in 8 colors.

  I just love the retro look of only eight colors.
  

• Made my first PCB

  Hacker404 • 04/09/2015 at 12:00 • 0 comments

  I started designing a PCB in CAD. I realised that it's not so easy to deal with these chips on a single sided board. The routing is a challenge.

  After a little while I decided that instead I should start with something simple as I have never designed / made a PCB before.

  I designed a tiny adaptor board to mount a SOJ36 chip on a standard width (0.6") DIP.

  I chose the SOJ as that's about the hardest thing I am willing to try to solder. and I chose the 0.6" width to make is so cramped that trace widths and spacings are a challenge. I didn't expect it to work out but I did expect to find the limits.

  The pins aren't in the correct order as there simply isn't enough room on a single sided board. That doesn't matter that much when it connects to CPLD as I can just fix the ordering inside the CPLD.

  Here's the CAD -

  The traces are 10 mill and the spacing goes down to 15 mill.

  Here is the toner and TRF transferred to the board -

  The TRF didn't bond propperly in some places. I am not sure why.

  Here is the etched / drilled board -

  It has a few pits but I expected that for a first run. The fact that the TRF was missing in places didn't make any difference.

  I tinned it with a big blob of solder then cleaned it off with solder wick -

  I soldered the chip on and then the header pins. I then tested for shorts and that everything connects as it should ... all good -

  After taking this pic I realised how much flux is still under the chip. If I clean that out it may even work!
  

• Preparing to use the Altera CPLD

  Hacker404 • 04/09/2015 at 11:37 • 0 comments

  I started checking the Altera CPLD boards I bought on ebay.

  These are the boards -

  Both boards are identical. The only difference being that one has an EPM240 chip and the other has a EPM570 chip.

  Unfortunately they shouldn't be identical as the EPM570 has four less IO pins. This is because four extra pins are used for core Vcc (2 pins) and core ground (2 Pins).

  There are four 0 Ohm resistors (links) missing on the back of the board. I just used wire links to replace them. R2, R3, R4, R5

  C1 and R1 are for an asynchronous power up reset. I didn't bother with them as I wont be using them.
  

  I also noticed an error on the silk screen here -

  What is marked as pin 59 on the silk screen is actually pin 61 of the CPLD. Pin 59 is *not* an IO pin, pin 61 is an IO.

  I then made a PCB library component to represent the board -
  

  So now I am ready to go with making a PCB board (hopefully).
  

• FLASH Chip Programmer

  Hacker404 • 04/02/2015 at 02:45 • 0 comments

  I decided that at some stage I need to get some code into this project. I was previously thinking of using an atmega to load boot code to the CPU and then have the CPU boot to SD card.

  I am not so sure about using an atmega as a co-processor now that I have decide to use a larger Altera EPM570 CPLD (about 440 macro's).

  In any case I need something to get started without going to all the trouble of writing boot loaders.

  I decide to hunt around the house for some FLASH as I haven't purchased any.

  I found 3 x 32 pin PLCC FLASH chips. 2 were in old mother boards and one was in a CD ROM.

  The main board ones were 3.3 Volt only so they were no good to work with a 5 Volt CPU.

  The CD ROM one was 5 Volt but it was soldered in -

  So I put it (upside down) in an oven tray and heated it until it dropped off the circuit board.

  Then when I looked up the specs I found it has the worst of both worlds lol. It has write protection so you can't flash it like you would with older PROMS (just as if they were slow RAM) and also it has *no* Low Pin Count (LPC) interface so I have to use a full blow parallel interface to program it.

  I don't have a programmer so I started hunting around to something to expand pin count (like serial in parallel out shift registers) but no good. Then I though ... what about the old Xilinx XC9572XL development board. I could connect that to something ending in 'duino.

  As it turned out the the stupid adaptor (dam I hate strip board) that I made was perfect. When I made it, I added extra rows of connectors for different sized breakouts / adaptors. A ZIF socket fitted right in and I had a PLCC32 to DIP adaptor.

  The stack -

  The stack from bottom to top -

  • Xilinx XC9574XL development board (5 Volt tolerant 72 Macro's)
  • The stupid adaptor that I made to allow connecting CPLD to chips etc with jumper lnks.
  • ZIF Socket
  • PLCC32 to DIP adaptor
  • The target FLASH chip

  I though of perhaps making another adaptor to plug this whole contraption into an Arduino UNO but on second thoughts that could cause problems (Stack Overflow??).

  Just to see if I got all the connections right and the constraints file right I just quickly changed the old video-out VHDL to work with the FLASH.

  Here's what I got -

  The lines in the picture are because the FLASH chip is much smaller than the SRAM and doesn't have enough room for a full screen.

  Then I wrote some VHDL to use the CPLD board as a big shift register. The code is at the end of the log.

  It's actualy two shift registers. One is A0-A16 (128KB) + CE + OE + WE + Data out D0-D7.

  The second shift register is to read back data from D0-D7.

  It has 4 signals to go to the 'duino. Clock, Load, Data Out, Data In.

  I am only new to VHDL and I couldn't get LOAD to be asynchronous so it is synchronous to the rising edge of CLOCK. I also had trouble with the tri-state dat bus and I fixed that by using a dedicated 8 bit register.

  I am now writing the code for the 'duino to program it and I will update that when it works.

  VHDL -

  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;
  
  -- I couldn't get a asynchronious load to work so load ended up syncronised to the rising edge of S_CLOCK
  -- use process ...
  
  -- note shift register does NOT shift when S_LOAD is high
  -- S_CLOCK is rising edge triggered
  
  -- **read flash**
  -- serial input WE(1),OE(0),CE(0),-,-,-,A0-15
  -- raise S_LOAD, toggle S_CLOCK
  -- wait
  -- toggle S_CLOCK
  -- lower S_LOAD
  -- serial read D7 - D0
  
  -- **write flash**
  -- serial input WE(0),OE(1),CE(0),-,-,-,A0-15,D0-7
  -- raise S_LOAD, toggle S_CLOCK
  -- wait
  -- perhaps do a readback to confirm
  
  -- **erase flash** as above
  
  entity flash_prog is
      Port (
             -- FLASH pins
             CE      : out    STD_LOGIC; -- Chip Enable   output to FLASH, active low
               OE      : out    STD_LOGIC; -- Output Enable output to FLASH, active low
               WE      : out    STD_LOGIC; -- Write Enable  output to FLASH, active low
               A       : out    STD_LOGIC_VECTOR (15 downto 0); -- Address bus output to FLASH
               D       : inout  STD_LOGIC_VECTOR (7 downto 0); -- bi-directional Data bus to FLASH, controlled by OE
               -- Serial...

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