Using the 18KHz clock source, the cascade of dividers is more complex than with the usual 32768Hz crystals. Normally, 15 stages of division by two (15 flip-flops) bring the 32KHz input down to 1Hz. At 18KHz, a different cascade is chosen:

1. divide by 8 (3 flip-flops) : 2250Hz
2. divide by 15 (3 flip-flops) : 150Hz
3. divide by 15 (3 flip-flops again) : 10Hz
4. divide by 10 (5 flip-flops in Johnson counter configuration) : 1Hz

The divide by 8 has already been implemented.

From there the 10-states Johnson counter was rather easy to implement.

Now there is a new logic design problem to solve : how to divide by 15 ?

These divisors have been chosen because they use most of the coding space allowed by 4 bits, only one code is lost out of 16. This is pretty easy to do with a synchronous counter : detect the code 15 (1111) and trigger the reset.

Detecting the code is easy too : just use 4 diodes (or even MOSFET) wired to the right signals, add a pull-up(/down) resistor, and you have a pulse.

The problem is with the reset signal because there are many timing issues with a ripple counter. Some kind of resynchronisation must be performed.

• Either the circuit must be fully synchronous
• Or the reset circuit must be sampled.

The choice will depend of course on the complexity and parts count.

A fully synchronous circuit is possible but implementing the incrementation with discrete MOSFET is going to be too heavy. The ripple counter has this amazing property of avoiding explicit calculations, which saves many parts.

Sampling the reset signal has been done before : The 10TFF cell contains 2 sampling circuit for D and /D, made of one P-FET (a pass-gate) and two N-NET (one charge-memory and one clock-enabled pass gate).

As is, the circuit can't be reused because the body diode of the P-FET will allow the N-FET charge to be removed as soon as one of the 4 FlipFlops is cleared, which might leave the others still in their previous state. The charge must be preserved longer and the parasitic diode must be disabled. This is possible at the cost of one more P-FET in reverse with the data-pass-gate.

This way, the reset signal will be applied strongly, during one clock phase, with only 4 MOSFET, 4 (more) diodes and 1 resistor...

The fanout of the clock is almost 20 FET gates. This is why there is a 2^3 predivider after the crystal oscillator.

The reset detects code 1110, but this could actually be 111x, so we can save the diode connected to /Q of the leftmost flipflop.

Update (20160519): the power losses through the pull-up resistor can be reduced by enabling the power when the last couple of FF are "ready", through one or two BS250. This would make a diode-transistor logic AND gate...