The "KCL structure" (covered there) is such a nice, regular circuit but it requires a mod 5 prescaler to convert the 18KHz source to 3600Hz. I have tried to make such prescaler but I was not satisfied.

5 is such an "inbetween" number, just after 4 (which requires 2 FlipFlops) and 6 (which requires 3 FF but is very easy to do with a Johnson counter). The previous approach with a reset adds nagging timing issues. So I went back to the sketchbook and made a few diagrams. I ended up with the following circuit with 3 10TFF and one NOR gate (with complementary output).

This is not an absolutely minimal circuit, when counting transistors, but it's simple and totally synchronous, which reduces problems and debugging at high speed. No reset is needed, which also simplifies the design, and it gracefully recovers from errors.

This is actually a "modified Johnson counter", I started with a mod 6 counter and removed one state.

1 2 3
0 0 0 #0
1 0 0 #1 
1 1 0 #2
1 1 1 #3 => removed
0 1 1 #4
0 0 1 #5

The new succession of states becomes:

1 2 3
0 0 0 #0
1 0 0 #1 
1 1 0 #2
0 1 1 #3
0 0 1 #4

Drawing the complete state machine gives the following diagram:

The absence of forbidden state (as in a LFSR) or subcycles of lower size makes a RESET input useless.

Implementing a NOR gate requires 2 P-FET and 2 N-FET, the inverter adds another complementary pair so the "cost" is 6 transistors. It's not the absolute best solution but I think it's so elegant that I adopted it :-)