testbench.v

The normal testbench. You only need this file if you are not using EDAPlayground as a simulator (since the file is already there).

x-verilog - 500.00 bytes - 06/21/2018 at 22:20

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testbench-display.v

Alternate testbench that adds $display statements. This isn't as useful on EDAPlayground (although it does show up in the console), but if you use your own simulator it shows how you can do essentially "printf debugging" in your testbenches.

x-verilog - 710.00 bytes - 06/21/2018 at 22:20

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design.v

The actual adder design. You only need this file if you are not using EDAPlayground as a simulator (since the file is already there).

x-verilog - 740.00 bytes - 06/21/2018 at 22:20

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