Variable Voltage Controller

• Called Power Multiplexer circuit, not Selector Circuit
• Basics of Power MUX (Rev. A)
  • Circuit I made is based on Automatic Discrete Power Mux with Priority in Figure 3-1
• Basics of Ideal Diodes (Rev. B) - Will be a useful read
• R10 is there to ground node B if the Buck has an Capacitive output impedance, this will prevent the non-inverting input of the comparator from floating
• **Original used MAX9095 as the comparator but it wouldn't go high for some reason

• Help with PMOS behavior issue for power selector circuit : r/AskElectronics
• For a nmos, due to the body diode, it will conduct current if Vs >> Vd, even if the gate is "Low".  Vice versa for PMOS

• Updated simulation schematic to better reflect the hardware implementation
• Made a table of the different states the power selector can take, along with the expected output
  • ***Depending on the design of the buck converter, the output impedance when it is not receiving power can be so high it is basically an open circuit or "low"
  • Either way, you don't want to develop a potential at the output terminal if it is disconnected from it's own power source
• Will make a separate file for each state instead of trying to simulate them in the same transient simulation

- get's rid of bi-directional issue without decreasing Vo

• Don't have the same bi-directionality issue that FETS possess
• However, they have a higher on state resistance
  • Vo(FET) ~= 2.299
  • Vo(BJT) ~= 2.28__

• This is where I noticed the issue of the MOSFETS Bi-directionality
• Never actually "electrically disconnected" voltage sources from circuit -> likely created erroneous results
• Later tried using the voltage controlled switch "SW" that is native to LTSpice, set Ron = 1 ohm and Roff = 1/10/100 Mohms
  • Not sure how to explain it, but there may have been some "odd behavior" with this set up, however I do not believe it is worth my time to look into this

• For whatever reason, generic transistors in LTspice (pmos, nmos, npn and pnp options) have a large on-state resistance
  • Whenever I am simulating a transistor circuit ALWAYS use a real transistor to avoid "weird" simulation results
• ***MOSFETS: both pmos and nmos, are really bi-directional devices, while, for example, nmos transistors are suppose to have current flow from the drain to the source, if the voltage at the source is higher than the voltage at the drain and the gate is high, then current can flow from the source to the drain.  Vice versa for pmos transistors.
  • Need to place two transistors, of the same type (2nmos or 2pmos) in series with their sources connected to prevent this

• Making a circuit to automatically select the 3.3V power source:
  • Buck converter as priority
  • ***Input impedance of buck-boost converter's output pin will vary based on the design of the buck converter.  It could range from very high (practically open) to low (due to passive paths or body diodes)
    • Applying a 3V to the output of an unpowered buck-boost converter, i.e. a pre-biased condition can harm the IC unless it is explicitly designed to handle pre-biased conditions
• Testing circuits in LTspice to see what works

• Decided on STM32G030F6P6:
  • ROM: 32KB
  • RAM: 8KB
  • Up to 64MHz clock speed

• Finished First draft of requirements document:
  • Input voltage range is now 5V to 10V
  • Output voltage range is now 0V to 20V
  • Must be able to deliver 500mA at 20V to an external load
    • i.e. Output 10W
  • According to ChatGPT microprocessor should have at least:
    • 8-16MHz clock
    • 32-64kB or ROM
    • 4-8kB of RAM
  • Use at least 10 bits for ADC
  • Update display 4-10 times per second