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Current Project Status
=== Prototype ===
Circuit Design -------------- ( ✓ )
Breadboard Proto -------- ( ✓ )
Power Analysis ------------ ( ✓ )
Firmware Dev -------------- ( ✓ )
Perf Board Proto --------- ( ✓ )
Deploy ----------------------- ( ✓ )
=== REV0 ===
Case Development --------- PENDING
Solar Feasibility -------------- PENDING
R&D Misc ---------------------- TBD
Schematic --------------------- PENDING
Layout -------------------------- PENDING
Documentation ------------- PENDING
Bringing up a new revision always reveals some new bugs. While the core logic of REV00 is solid, I’ve had to perform some bodge work to get the system fully operational. Here is the breakdown of the primary issues discovered during bench testing (in no particular order). Items below are all listed in my REV00 errata, and have been addressed by my REV01 update.
This was an easy one... I neglected the pull-up resistor on the UPDI line. Easy to solve with a 10k.
While testing the drain on my pulse energy storage circuit I noticed self discharge was much greater than expected. Current was either leaking back into the boost converter output or across the H-bridge.
Luckily past me saved present me's bacon. Somewhat anticipating this issue, I added a 0ohm resistor at the boost converter output. Replacing the 0ohm 0603 with a Schottky resolved the issue.
Now when the boost converter is disabled the voltage across the capacitor holds steady.
The system refused to boot from VBAT. Whether I simulated an "already charged" battery, or if I allowed the system to charge the battery itself, VSTOR refused to come up. Instead getting stuck around 1.6V.
I initially suspected my voltage divider values on the TI BQ25504, but they seemed to match the schematic. After some datasheet sniffing, I found a critical note.
If a system load tied to VSTOR discharges VSTOR below VSTOR_GEN or below VBAT_UV during the 32 ms initial MPPT reference voltage measurement or within 110 ms after hot plug, it is recommended to add an external PFET between the system load and VSTOR
It seems like the BQ25504 is extremely sensitive to VSTOR loading during startup. I found that if I hold the solar panel directly against a bright light source, it drives VSTOR hard enough to overcome the meek ATTINY load. Once the system is past that 110ms window and fully booted, it functions normally without the extra light.
The datasheet recommends adding an external PFET between the system load and VSTOR to keep the rail isolated until VSTOR is stable. I'll be implementing that to ensure the system can boot on REV01.
This was a "head-in-hands" moment during sparkup. I designed a voltage divider to measure the 24V VCAP signal, but I used a low-side switch (SNS_VBST_EN) to enable the measurement.
When the low-side switch is OFF, the bottom of the divider floats, and the ATtiny1616 sees the full 24V signal (heavily current-limited, but still). I essentially slapped a high-voltage rail directly into a 3V GPIO. Probing VBST_DIV showed it pulled to VCC (3V), meaning the internal ESD diodes on PA5 were working overtime sinking about 60uA. Not ideal for long-term reliability or power consumption.
For the next spin, I’ve added a high-side switch with an NMOS driver. Because of the double inversion in the hardware, the firmware logic remains identical. Easy peezy.
The goal for this test was to verify that the overvoltage and undervoltage protection limits for the energy harvesting subsystem are hitting their intended set points.
Result: PASS
| Test | Expected [V] | Observed [V] | Error [%] |
|---|---|---|---|
| Overvoltage | 4.133 | 4.15 | -0.4% |
| Undervoltage | 3.040 | 3.06 | -0.6% |
To simplify this test I isolated the solar harvester from the system, and provided a relatively small capacitor instead of a LIPO or LIC.
For this capture, I probed Vsolar, Vbat, and the current into Vsolar. (Schematic above)
I was hoping to catch a glimpse of the MPPT (Maximum Power Point Tracking) at work here, but no dice. I suspect with a better light source I’d be able to witness the MPPT in action.
Using the same setup, I moved the VSOLAR probe to VSTOR to observe the disconnect behavior.
Now that the limits are verified, I can move back to full-system integration and see how these limits hold up under the varied load of the H-bridge pulses. For now I'll be testing with bulk caps in place of a LIPO. In the future these limits will likely be tightened further.
I was bad and didn’t push my test results. Yikes…. Doing this retroactively now.
With the REV00 boards in hand, it was time to move on to hardware validation. I had a slew of tests I wanted to run, but at the top of that list was testing the new pulse generation circuit. This includes the bulk cap energy storage, H-bridge, and output current limiter.
The primary goal for this testing was to verify the circuit design and add any findings to the errata. So long as the solenoid toggles properly, I’d consider it a PASS.
First, I needed to write some firmware for toggling the H-bridge. At this point, I had already developed some code for an ATtiny dev board, so this was a pretty quick task. For early testing, I’m just using a dumb delay; in the future, this will be replaced with a proper sleep method.
Initial No-Load Observations
During this test, I had the bulk caps powered continuously from the boost converter. Findings below.
Jesse Farrell
_delay_ms() is significantly off on this implementation. Since I'm moving away from this for later revisions, I'm not going to lose sleep (😉) over it yet.Before connecting the solenoid, I wanted to see if my current limiting circuit could actually limit properly. I used a current sense amplifier and a variable load across OUTA/OUTB. During this test, the boost converter was continuously enabled.
| Load Resistor [Ω] | Peak Current [mA] |
|---|---|
| 10Ω | 512mA |
| 5Ω | 552mA |
| SHORT | 568mA |
Since this current limiter relies on the Vbe of Q12, I was curious how bad its thermal influence would be. For a quick sanity check, I held a soldering iron set to 750°F (400°C) about 1cm away from Q12, then nearly touching the transistor's SOT-23 package.
The expected temperature coefficient for Vbe is around -2mV/°C. In this system, that translates to:
-2mV / 1.35Ω ≈ -1.48mA/°C
Based on the 50mA drop, I only actually increased the die temperature by ~33°C. I suspect the PCB was pulling heat away from the chip better than I originally anticipated (still 33'C seems low). I’ll likely need to revisit this and saturate the whole system at Tamb in the future.
Now for the real test: the Rain Bird TBOSPSOL 9V latching solenoid.
Initially, neither the positive nor negative pulses would engage the solenoid. The current limiter (set to 500mA) was working exactly as designed (which was the problem). After checking the coil resistance, I realized it's only 4.7 ohms. At 9V, that’s a theoretical draw of 1.91A! My 500mA ceiling was starving the actuator before it could flip.
To get around this, I shorted R50 with tweezers to bypass the limiter. Afterwards, both positive and negative pulses worked perfectly. I’ll be removing this output current limiter in REV01.
Analyzing the switching cycle reveals some interesting physics in the H-bridge:
I wanted to order this earlier in the week so I could debug the hardware over Christmas.... From my experience a JLC PCBA takes 2 weeks to arrive on my doorstep in the best case. I'm not sure what sort of down time they have over the holidays.
With Christmas PTO fast approaching I thought I’d focus on finishing up some projects. My goal is to order PCBA to tinker with over the holidays.
A quick overview of the “WellWatch” project. This widget essentially just monitors a float switch/gauge and toggles a solenoid accordingly (see the project homepage for why I’m doing this). Some challenges that make this project a bit more interesting is (1) the system will be operating from a Solar cell, and (2) it will support a variety of switching voltages.
The core blocks of the system are shown below and include Power (PWR), Microcontroller (MCU), Pulse storage, and H-bridge.
MCU - The microcontroller block contains an ATTINY1616 which; controls the H-bridge circuit via SOpen and SClose (solenoid open/close), senses the state of the float switch via GPIO_HI, GPIO _COM, and GPIO _LO, and measures VBAT as well as the pulse energy storage capacitors.
H-Bridge – This circuit is fairly generic. The only slight deviation from a jellybean H-bridge is the addition of Q6 and Q5 which allows me to control all 4 driver FETs with two signals, OPEN and CLOSE. I still need to fine tune my component selection to reduce the leakage presented to the PWR input.
Pulse Storage – This is another energy storage circuit (not the LIPO battery!!) which provides the 50ms (typ) pulse of current required to toggle a latching solenoid. The schematic shows two active current limiting circuits. Capacitor charge current is limited by Q11/Q9, and capacitor discharge current is defined by Q10/Q12. Charge current will be configured to align with the capabilities of the boost converter, and the discharge current will need to be configured for the selected solenoid.
Anyways… that’s the circuit and here’s the PCB I developed this weekend. I’m just working on some final cleanup. I also need to add a few extra 0ohm resistors to isolate each circuit block. Jumpers are great for debugging and general V&V work for an early design.
One last thing… If you’re wondering why I set the board outline above, plan to assemble the project in this enclosure from polycase (https://www.polycase.com/wc-20). The LIPO battery is harvested from an old “disposable” vape. My current plan is to rest it ontop of the northern end of the PCB (TPs will need to be removed later). I still am somewhat debating using a LIC instead of a LIPO, but for now I’m prototyping with a LIPO.
Its summer again, so the priority of this project has once again been bumped to the top of my list. Funnily enough the prototype project started just last week one year ago… in my defense though I was busy last weekend, if not for that maybe I would have done my first revisit post EXACTLY one year later.
I fell deep into a power budget rabbit hole this weekend...
I’ve been interested in hybrid capacitor technologies for some time now, and this project presented a perfect opportunity to evaluate one on paper: the Lithium-Ion Capacitor (LiC). Compared to conventional lithium polymer batteries, LiCs offer some intriguing benefits. However, their primary drawback is energy density, which is lower than that of a lead-acid battery.
My goal in this post is to investigate the feasibility of using a LiC for energy storage in this project.
To evaluate whether the lower energy density, and therefore reduced capacity, of a Li-Ion capacitor is feasible for my application, I needed to model the stored energy in the system over a full 24-hour cycle.
The model had to be detailed enough to capture subtle droops in stored energy. This allows me to then assess voltage margins ensuring that the system remains operational throughout the day. In particular, I’m focused on tracking the minimum voltage across the energy storage element.
Irradiance Waveform
To begin modeling the solar input, I approximated the irradiance over a 24-hour period using I(t). Using a sunrise at 7 AM, sunset at 5 PM, and a peak irradiance of 800 W/m², resulting in the below plot…
To validate the model, I compared it to real-world data from a nearby Ecological Reserve. The overall trend aligns well (Albeit less noisy).
From Irradiance to Power
Next, I converted the irradiance to instantaneous power using the specs of the SP-53X30-4-DK solar panel. While the datasheet reports its dimensions as 53×30 mm, the effective area seems to be closer to 48×25 mm. The devices maximum output power is 0.21W, and its efficiency is 18.6%.
The instantaneous power equation becomes….
Solar Power Over Time (Energy)
The energy provided by the solar panel will be the area under the curve of P_{solar}. Desmos has an integration function, but I find it causes the system to lag badly. Doing this by “hand” I get the equations below. We have to be careful with the start and stop points of our integration, since the solar panel will (obviously!) only provide power from sunrise to sunset.
Model Assumptions
It’s important to note the approximations made by this model. Critically, I’ve ignored the efficiency of the energy harvester IC, and I’ve ignored several nuances of the solar panel such as thermal influence and MPPT (maximum power point tracking).
Now that we’ve characterized the incoming solar power, let’s turn our attention to the main energy consumer, the solenoid subsystem.
Every <to be determined> seconds, the system updates its state. During this update it sends a 50 ms pulse to either open or close the solenoid. Each time drawing 2.5 W, which equates to 0.125 J of energy.
Assumptions
Luckily modeling this system is very simple, so long as we allow ourselves a few assumptions. Assuming the energy required for a single pulse (0.125J) is insignificant compared to the total energy in the system, then we can say that the drop in energy, and more importantly voltage, from a single pulse will not appreciably affect the system.
Let’s test that assumption with some numbers…
Assuming 1F at 1.5V, a single solenoid pulse will drain the stored energy to 1J (0.5*C*V^2 - 0.125J), which will result in a drop from 1.5V to 1.41V....
Read more »I've been working on the REV1 enclosure and had to brush off some old CAD skills. Whenever I do 3D modeling I try to do lots of simple test prints... Measure once, print twice I guess. It's much faster than printing the final enclosure and really helps tighten up the design feedback loop. Below are 4 simple test prints, followed by the first prototype of the full enclosure.
The enclosure will need to be water tight. Water might leak at the (1) lid-case interface, (2) solenoid-case interface, and (3) through the case itself. To avoid (1) I'd like to use either a o-ring or some type of silicone/epoxy in the groove along the top of the case. For (2) I can easily put an o-ring around the base of the solenoid. And to avoid (3) I'll need to coat the cavity with some kind of a sealant, since PLA isn't exactly water tight.
The prototype was successfully deployed, and just in time too, as you can see the well was flooded again when I arrived. The setup is very make-shift, but only needs to work for 2-months. I’ll continue to work on a more polished design for next summer.
There were a couple integration headaches to deal with, mainly finding couplers to connect the hose to the ½’’ pipe threading on my solenoid. Even with the couplers, the hose was fairly leaky so I’m a bit worried about water getting into my enclosure. Luckily I had some marine sealant/epoxy.
For the next (non-prototype) version I think I’ll try to mount the PCB directly to the solenoid and place a gasket against its side to seal it off. I’ll also need to find a better way to set the float switch’s position. I’m designing a PCB on the side here, so once I’m about to order I’ll post an update. I expect it’ll take awhile though, especially since I have to do some 3D modelling.
How will I power this board? I need at least 5V for the solenoid, and the ATTINY can run off 1V8 to 5V with varied restrictions to its performance. Ideally, I’d just include a low quiescent buck-converter to converter a 9V battery to 5V for the whole system. Sadly, I don’t have a converter handy in my parts bin, so here we are…
The solenoid was handled in by the original circuit posted here. 9V Vbat will be current limited to ~500mA regardless of the input voltage (within reason!). That leaves the ATTINY and a 9V battery, with no on-hand switchers or even LDO’s that fit the bill. All my LDO’s either didn’t support >7V input, or had a minimum load requirement that would squash the battery life of the board.
What I did have on-hand was a boost converter (BU33UV7NUX) on the same dev board as my ATTINY. So I decided to add another battery, two actually (2x AA). This new battery will feed the boost converter that will generate a 3V3 supply for my ATTINY. The boost converter can operate all the way down to 0.6V!
Sadly, this plan didn’t last long...
So, I immediately killed my boost converter dev board *face palm*. I hummed and hawed for a while and decided to do something dirty, but easy. Why even bother regulating the supply! Two double A’s will get me around 3.2V -> 2.4V during their discharge. That’s well within the operating range of my ATTINY. I tested the circuit at the new range of Vin, and everything was still functional.
Here’s the system running off battery. Everything’s working okay, though at higher quiescent currents then I measured previously. Originally I measured <1uA on the ATTINY, but now I measure 300uA. I suspect I tweaked something in my code during debugging. I’ll hunt this down later. (even at 300uA the current draw isn’t enough to drain the device over the summer, so I could leave it as is… seeing as this is just a prototype).
I always regret going down the perf board route. Too many flywire’s and last minute bodge jobs. But since this project is on a timeline, I don’t have much of an option. The circuit hasn’t changed from the last picture, but now includes an ATTINY1616 to tickle the various control lines. See my first project log for the circuit.
I decided to first sketch the circuit out to roughly floor plan the parts & wiring. The final result looks a bit like the ramblings of a madman, but thanks to the floor planning there were no major miswirings or debugging required.
And here’s what that looks like in reality…
I quickly ran into an issue with the ADC leakage current. The leakage current from VBAT to PB3 through the 1Meg resistor, pulled the measured signal down to the almost nothing. In the future design I’ll include a buffer to resolve this issue… but for this perf board version I might just ignore the feature. TBD.
Bud Bennett
Ted Yapo
BleakyTex
DrYerzinia