Close
0%
0%

DTAP2-ULSR

Universal Latch-based Shift Register. Still not JTAG and fewer pins

yann-guidon-ygdesYann Guidon / YGDES
Following
Liked Like project

Just one more thing

To make the experience fit your profile, pick a username and tell us what interests you.

Pick an awesome username
hackaday.io/
Your profile's URL: hackaday.io/username. Max 25 alphanumeric characters.
Pick a few interests
Projects that share your interests
People that share your interests

We found and based on your interests.

Choose more interests.

OK, I'm done! Skip
Public Chat
Similar projects worth following
57 views
2 comments
1 followers
View Gallery
Public Chat
This is an interface, protocol, circuit and method for the control and inspection of logic nodes buried inside an integrated circuit.
Like JTAG, it is a shift register and can do boundary scan.
Unlike JTAG it can't be chained between chips and it's not as fast.
And better than JTAG : it requires only 2 input pins, it does not consume high-fanout resources (nets and drivers), reduces the internal routing pressure and does not interfere with existing critical designs.
Output is optional.

20260913 : https://github.com/ygdes/ULSR_demo

...

This is a new generation of Debug and Test Access Port

See the previous generation at https://hackaday.io/project/193122-dtap-debug-and-test-access-port

This one though is simpler (less convoluted) while keeping the main advantages and reducing the pin count : only 2 input pins are required. Their names SD and SC are kept, partly for historical reference.

The shift register uses a different type of bit : pairs of latches, instead of D Flip-Flops. This creates new opportunities to regenerate control signals inside the chip, beyond the input pins : some sequences of pulses extend the basic functions.

  • A single bit shift operation is a pair of pulses : SD SC
  • When SD and SC are asserted simultaneously, the shift register is fully transparent : the input value is copied to all the registers in the chain.
    This is the condition for RESET : SD+ SC+ SD- SC-
    For this to work though, the input value must be well defined.

We can observe that that if we repeat the pulse on SD or SC, this does not affect the state of the shift register / scan chain. The new general rule is : a full sequence contains any number of pulses on SD followed by any number of pulses on SC.

  • During and after reset, a Data register (DFF) is cleared. It is toggled for every pulse on SD. Hence
    • To input a 1, the sequence of is SD SC (since the first pulse on SD will set the data bit)
    • To input a 0, the sequence of is SD SD SC (the second pulse on SD will reset the data bit)

Price : one DFF

The data input is indeed regenerated inside the chip, without all the complexities of I2C for example.

But by sending more pulses on SD and SC we can create more control signals.

If you send 4 SD pulses, a second DFF will toggle the "Latch-out" control signal, that holds the bit values for an outside circuit:  (circuitjs)

Total cost : 2× DFF and one A22O

For input, the same idea is recycled but on the SC pin with 3 pulses. Special "input" cells get a pulse from a pair of DFF:  (circuitjs)

Cost : 2 more DFF and a AND2.

Both can be combined and chained at will.

And the In and Out cells could also be combined.

(note : the latches here are MUX2 with loopback but that's just an artefact of CircuitJS, actual implementation is different)

.

TODO : for each SD/SC sequence, toggle the Address/Data flip-flop.
.

.

Routing trick and blocks

Speed is not a goal. Exact synchronicity is not an issue because clock edges have disappeared.

Blocks with inputs and outputs can be scattered across all around an IC's surface in any order. Each read or write block will contain their own control DFF to recreate the control signals, saving global routing resources.

.

Each block or functional unit is chained and the SD and SC are buffered, becoming logically separate for the synthesiser and P&R tools. They are demoted to simple point-to-point data wires that do not need extra special handling, thus liberating surface and buffers for the actual important circuits.

In contrast, JTAG requires high-fanout resources for TCK, load_enable and store_enable nets, as well as clock tree balancing to keep all the signals strictly synchronous.

  • Power on reset and external pull-downs

    Yann Guidon / YGDES • 14 minutes ago • 0 comments

    So now, RESET is not a level-triggered signal but a sequence.

    The previous scheme was to implement weak pull-ups on SC and SD to force it by default. Convenient, simple and no fuss.

    But the last log Direct read / flow-through adds a new wrinkle.

    The DTAP has several constraints, such as

    • It is independent from system reset or system clock, the DTAP may not rely on their presence to initialise.
    • All latched values in the chain are unknown and considered random at power up. There is no known/safe way to have a register powering up to a given value (except with the reset input).
    • The whole circuit must be able to work when the DTAP is not connected or in use. The system under test must be autonomous and may not rely on the presence of a DTAP controller to initialise.

    A pair of weak pull-ups is still "safe" but its actual effect is unknown. Except that in all cases, if you take most cells in the chain, their values will be the same. Which is a condition that can be easily tested.

  • Direct read / flow-through

    Yann Guidon / YGDES • 5 hours ago • 0 comments

    In our series "yet more things that usual scanchains and even JTAG can't do", here comes...

    .

    .

    There are 4 sequences that produce overlapping pulses, and one of them is chosen for RESET.

    An overlapping sequence makes the whole shift register "transparent", which is useful for the RESET cycle, but can also serve other purposes.

    RESET is defined as SD+ SC+ SD- SC-

    Now, what if there was a sequence SC+ SD+ SC- SD- ?

    • Capture would not be affected because SD=1 resets the counter.
    • The Update counter is reset too
    • But the Update signal is active when SD=SC=1.

    Apart from the last point, nothing changes, the chain is flow-through.

    Now what if we could tell the overlap is a reset command or not ?

    In the chain, a given set of cells can act as MUX such that a given signal is not only captured, but directly read (through the rest of the chain) and observed in real time, for onchip debugging.

    Inserting a MUX in the scan chain is easy, the control though is not. There needs to be a "update" cell (3 latches) controlled by the update counter, which can itself be reset. So there must be an extra state bit that tells if an overlapping sequence is a reset or flow-through.

    Two bits of "update" can select among 3 sources, and default to normal chain upon reset. So there's now a MUX4 with 3 state bits.

    .

    .

    Decoding a RESET and a read-through is a circuit called "phase discriminator", I think, it's common in position encoders (mouse wheels etc). It's quite simple to do, one gate and two DFF.

    CircuitJS

    One can easily notice that the sequence at the start matters, but then it can end in any of two ways without difference. This could be used to send more pulses, to select a different signal source.

    In the following circuit, a Johnson counter selects one out of three sources to insert in the chain.

    But the control logic becomes more elaborate, as the number of signals to observe increases, so the following circuit may look easier to implement:

    circuitjs

    wooops swap the MUX2 polarity...

    .

    Of course : the observed signal will be delayed "quite a bit" proportionally to the distance from the output pin so these stages should be at, or near, the end. But there is no strict requirement and it's application dependent so if the signal is slow, well, you don't need to bother. It's flexible !

    Anyway, can your JTAG system be used to select one signal for real time observation ?

  • Alternating polarities

    Yann Guidon / YGDES • 07/10/2026 at 12:55 • 0 comments

    The real circuit uses pairs of A21OI gates to create a latch.

    CircuiJS:

    Due to routing considerations (keeping the inter-latch wires on M2 but preventing crossings), the Q outputs actually go to /D and vice versa. It can create quite a confusion but since the latches come in pairs, the polarity is restored at every bit. It's easy to get confused though, particularly with the inter-macro connections.

    CircuitJS :

    (don't mind the mislabeled inputs)
    • So inside the pseudo-FF, the /Q output (controlled by SD) goes to the next Q input and vice versa.
    • Outside, the /Q output of the SC slice goes to the Q inputs of the output buffer (controlled by Pulse2/Update) and the Q input of the next SD latch.
    • In the layout, Q(SC) is tied to D(update), so the actual output is taken from /Q(update)

    .

View all 3 project logs

Enjoy this project?

Share

Discussions

Yann Guidon / YGDES wrote 07/10/2026 at 12:49 • point

version avec A21OI à polarités alternées

https://www.falstad.com/circuit/circuitjs.html?ctz=DwYwlgTgBAZgvAIgIwKgFwM6IAwDpsEECsqYIiSeATAVQOx0DM2AHFQGwCcndqIARoiLZUAB0EIALI1QA3CENQBbTEICmAWiQoAfACgoUYAHcoAD0QbOkyVE7soVpFTvtU8BCID0+wyfOW1rZIDlY2ru44CD4GRqYWCBp0LMGhQVAhkZ7RvnEBicm2GowuSSkZbrBRMX7xlnRELtiODS5INlneucAAggB2ACb5SewsGeEjY1SSIlXZNXkJk1DTzUmNK3RUnTmx-kvsMyssY8XYtlQnOwv7lpRbUJIhjvculyzX3XWJlKxQJWtfmNGClPntvhoUsCaC8CNDZh4uuDhlDjqdXmiwbVhoUoIcWuV2pIsYtLCxnviyrZDiTgAB5aBLVpoxyHZrvHZQAD2ihu-SGS1RzCKzOFnJ5CBINzMOJKKw4rKIUyonE5GDAiGmqDQakQogArgAbDBqbbSnGSUqSUJ0c6OaRqjUILXoXUIAAiYD6u2xgoIGUujhY-pKtIhweacqcLlDcyRvsCzn+pU4SZpcZ9RndADFDWBRLmuaJhqmXJSTs10x4zV9hkCA6dSw2w3W4Q3YX8AS2lhiNJSMRyMzdw89nKcI82h90ZYLbY4QaciEhGPPzlliVB1ZqNzrEBgABZgGBoKBejJQABcUAAyu6bwBhAA6fQPR5PZ+aV9vN7v16ffQNY01HPL97wfcC4AAMgAczQABuU8AP1NBn0Ak0VkvH8sO-b8oNghCuWQg00EzYAZzuGxQgXF4kE4UpGCVddUC3Z0dzdAAlNQTTQL93QAagfATbw0B8NGfUjyJ+doiHtawaPaWSUDmDcWJdXcEGzMAzAkksWFCSROBXMIkFkhFEBUp01LdNAlFEHSe0oRsinuRslI8Czt21N1b3su5ziKOStGwZ4nCYzdLLYxA-1IiFmSsUIJ3i7t6g2NY4vsZLEh4Bw0tSzLIXsF5AwKtJKkRGKcXKLRipYQrqo+KdkSZKqo1xer8sS1qWu2RqEx+VhTioIhQm0DYNCGsrqlrHtsGG+dGBG2bQgm-LuHohbYTm4oFvyyhpkcd5YROA6rl60ksuKw6rDok6GvKm4GVbP5xuOoLnqQOhJuybleW6R6Zoecatt7IlxV+vZJLe05pDSZJ7UYGRlOYiKvKi91SIAGRLG7trSHGni+2YlCURA0AgfU1ExktLteujocyDMoGJ0nycp80lnSDQYccVN9IRsLVMihBouHJ7Tijesxw6ur+2wQGqympq-OeqNaqonr7u6HM8wLQ0ixROq6r0gKvprJWss+x5JEbS2zPmac60oIpuaCy2uf5pHws810ovvKmZteq7HPpwmxAof27iQMaJposaCc5URw-ZyPRnhkbl2hj33OR731J85PEhYJgoGGhKiBk4bVTmSpBdRhAAEVfMLhpHjnSEiDoVvEezr3WLrxuC77FgV3LmS+3YCvGM92ufYbpuh84R5GBMvs6BM6QNw8GuUdngfpssdgHmttZD5cGw7sVvrV5cRpTlPx4MrO25Env4+Wg2AzQ9FpkP+DVkj8fprc26wb5JhAQ-L++8Cgf0pMyY+tIAByXJGQpRvsVe+t8OpygJkGa2jwGZAKvqiHBkI8HDTtvGc6pCxjkKDHKchtJ+Qomwa1D+sZCFGCQSg6BZ88HXythfb6EopTdCYYKehExmREA6IzYRFUObhFvjzcIgDL5UOygIuhvDBGUOftQ-Bi0j4ELUb0QYwxaHSOdn-SxiDkHDDfufe0-pz6MLMUsWh0grR-08WDSU8jLAdwcLQjQFj2AUP8YkQJBjHBRIYU-CEHiQpRPjk-Lh9jrHFRmM0TBsjwZXwcZSBxwZ8pvyXF45on8SneL-lzZxqj7bAKyY8GpDj6m6IhE0pRtSKltIid05pawmkuKfpDJ4ndpAr0YNwJem9EDb1zm6PeEN7HaBLuXechk1mCI8n3XefSLHoIeDkjheiPF8NftbXabYQRFCiTc-KdyqrJOMQ0q+woWRnFsCkk5EJDqOOKB-S58ThiHS6TckulxaSQ2XIvUeRUTLl22TnXZ6kll+GhZIGSEyirjMYLMhA8yUWLL6WOAZRUxjDJ+XWQMXTSWVOBT2QMb9xp-HpVSpYNAKU1Lpb07+lhOUlzAQKtlJjfmsspMK4pqS7Ecr+LSmlkKGX8uOiQ953zRXDDVSFd5cT2WWB1WE26JcwmuIFMqilUZhXsJMWk2VFK+F0qBeVH6fi+RuPNSXCYAqbG5NdaI91iRDrGwOn8Y2viRF7Ftfyv4n10SBljeG0iYiPVxQFa0fK7yKxGorBmu0TAqJ2hzUqwNx182rlsPm2x3CWVjFRPVKAUJ8ppqqgKiMTbQ2WtDS89pILQ3+nreSSBwDSWJVbd2klgY60jvHXyn4k7+2koTSMusmKoANBXs4TuDR8WEqsogNFRhoVTIbS3aqJki5It7nuues6Xq1r4eCxtxa71rtTgClwS69WJANWsd5lbn1RNtLcy2-6v1QzXXaEJIG1wAcNbG-+H7RgPMNXW++T6TmjNWUXMeUyVwXoFjvVF88xlrqXBsxe26si7qFgevRTTEpNM-RqpY9G+H0ZnVA-pDG-6Dqqc0Bj-pePPrfsPcpDaOONL-m1ETBAq3pP42xwTTqoguojVfWhZaoMOFA8xgJIGNpaYbVKsDUSs0hJQ8ZkxybIlwbjlJxoiabhRsSG-eD-SmOvKMNZ8z-HCk8YVp5vRqJNMYh04FiE6Q3OidfTopNAbIRymDeAsNvq1OcJlagmLCGYuOf9Wawuco4rMnTc+1EZnotFrA8FgzZXLPheYR+mreCwu6Oc8l85Dx0O6Z4WuqqzI23Pv66wlwQmwP9f7WhiTV80P9v61NqhaGOsjfm3ombJ8Hged0ZDUYFGyOrxMpR6uyLr20e28PE9Y92ATxPZemeRHB7YbXZwNYLAO5Pe7uZY7NH55Fzw3pIM6yThVy3l9-ufSNF1o0WE2Lt76zgvA0Bq5G2DMYnVYF7bdphpjyVEEpDR2r3fcHmEhw1pF4hJVVsAjCz93zwRjfK784FKVyo6DvZg8EZfLbsvEnTAqdEpp0T7AI3UwxPKLVHdrP7sOwOHmzg2P-t0E4LdwjxL2fLwbc9xneHDIs4J2DtXK5FdFGXjJRXvBp4q4F5x8FYLyjQ4zXb56UPWAlOcQ+wFMPrce-nBsNkrvsnFRt4qsDDEyxHDCNSGYq1whsmURWvHVXEt8Ih8p+rANShElhPLfFPaZrvTdvWYoGtusJbaCEG2DhtAJ5L+kewax0jBwzRsOvcfXDhNvaHrL7628O9sHTHmls6a94bQ+8oQ-l1LARiubQClihRwyNoc3Pc7uq+l-q9XzhKBa4DMuXXK+rfLJl8EUaovK-aGV9Tm9a+X5C53yvJUwQqDtD35bq-w65ZtCWlnxrQ6r71iAx2GMHtDnuDpbFXhXnYMHiYpDL9gGNgGXDJM4NgMDnMpLqvofmSC3DPi9m9jPh9lIGgQfuisMKMNPrRJdtdtoErnzidvPDthkHLCvIfCZPcBLnrmzpxvfNoDCPwo3s+lweXtltoDtPwQ8NwblGXiIWNhsOIUIcuL-lQsyKNKUEofIflKoZBqoTQHJj-GXm+gIdXmnmSHKJQFtKiKYQoUFnghYbgkATQO3pxuYfYVonAQ4XsN5tFr2EoR-joZlsHEIQNLlu4fFp4UgH1jIWESAapuDuEP4aXgwadFVtYV-q7J-sNKauYoauflYs0Nkb4S5n-HEU0nwSct5rQr2G-K8EEepmAc4T5q4Q8mASkVEkgW4eplkc0U0ekdKtWpUYIf0uAdUVQn0ZBn0docJoUVHGJsIZYR0pMTwcUWocJv6LIVzJMVISXosW+osRsUYS5isUgU4rkYERPpYCRvcJMtMqwS-pfqdisiweQRsmQdQRbrcfslkf0QYZ7sAuUQNAEYkSXpLELsBpXsCY0aCftIZhYbmrYGZu8tCc+odEUSsScWBkif0Vsd8cQT2MelQWPJvgvi8cvq-ncT2KuhcTigwXQGwfvm-n-oGKsaSiUYCQyf0UyUsWBuyTwQKjMe2kAYcfWryYiX8MoSGvybsbntGvyZBjyUgfkTWgvm+uyYYZKSWkASkfCUtDCQwVtPCfYdqa0Uaq0RkRysdL2DyT4T0b2uqa9EyaiSpnIm6vli+tkWKQvqCKln0o+opgplicMf6G5p3ptjEbYF0tFscorMAF4OABAPoEAA

  Are you sure? yes | no

Yann Guidon / YGDES wrote 07/02/2026 at 23:51 • point

3 gate macros :

https://www.falstad.com/circuit/circuitjs.html?ctz=DwYwlgTgBAZgvAIgIwKgFwM6IAwDpsEECsqYIiSuAzAEwAsSN2TSAnEkQGxE02ogAjREWyoADkIR0qqAG4RhqALaZhAUwC0SFAD4AUFCjAAggDsAJlAAeFbAHYaUJPcfaeTl6ngJRAen2GwAByAPbQNsgcjqx2nE40tFAxnF44qCGK-gZGZpYRzg5JnNhOUUWisGlZgQDu1rZcHgAcTR6Fzi2pPgjVRnX52I2sdHQejR1NXX4BffXILkkjY3HDdFM9M8Fhc26ug3GMic5c673A-RRlrKyuZc7Yk5XdZxeR7s50Jbse9Kebr997q1Dntfk9ptlzjsEnsHqV3sw1uCNpCATDlvEjoi-qjoVi4SCkrEcYEADI7fbNYGU3YkoxWClNJDw4FsVilTgoJ5IjBgRBgtBqRAAZQAFmAYGgoKSAIZoECilGBACyeOisXiTRKyTpwFV+XRxwONC1y11DINVHZrE4xqIdiKrC6KSgvP5SMFiAAikr6dCGB46Hb2R8ndzUG6EAKhQgfWcLbYqMybVRA9bbV0eXyox6Y3HNgn5kmPMM0yW7M6I9no97fcBC0gg6nnKXG0zy5XXdXc7X4zsm0SQ3R26wmnxw133ahPbG6w3OHZm9gg05OOw05mq1P0Hm5zsF8nbaumumw94XZGa7OzvqKLbRkanHZGGbkTf95xRskny+dW+CzsRBIM2HDApwxbaJym6Tjm04xmKEpSrK8qKmc5L5MO1ItE4mHwuO3gQrUH4PgQYGfkSLoEXWAL3hiSC0c4YJUS8xEeASRBNCRTFVP8gGcWxZFcUizG8fkHEkZ8TjiT8wk8biYn8dcrjSUCuqhOEFAqTSDH7LqAIiF+xQ4dhNoVCJ8kULhpnGVhjzmURGHYRMUnLlSuq5IBrnfqBX7Ev+kLqXxvkHLRf5UVAYCmIgMhQBkCAkGcHlia5BTKfxqXuRYnlfi+PlJIwelBflaWGWZclktlUAngcBlVbQ5qAcBdVgWwVUMNBl49ggADiahIXKCp1uhmleSaOGSTcdnlX6+RUEQqbsMCw7RDQXLeFm24zgAolYaC4FAAAicoylAACSphDRShTfkpFHrFAYgUJdAztJSt1Grqw3ILVj6NvQr72UYX0cF5Nw4f9Sn3Y9yB7gMVDNrwriGrwJATp1cH8gA61AxirQA8qdUC+FAMpwEgTS4HwfYYUgDqMLwq5g-TqPrVusE7oguNIATUAANQ47w3OE8TpMJLgKTU-yzBEPEDOIw+KMdd2GNSNjXM8yLcBUJw1DPRQNxfDSnGGyc-kVfkBsUU4xt3ciD1PZLyBNHYIbYK2J5027FZPBeysc9eAH5M76bNh7RSUYgG3szO+aQoWTAnoGcSrfYG5o37Mew1Lzvh1AKcyzaZ6IL7m27u+ESrWD1V5-QJTVbqt5RvRdfDjXkmcVNzyB-rNAhqBefLnT9FrZHbNXghkrSgNqGbMDrApQ8wLzw+USFRXDyG3CCfan5gNQuvpqPtvMlr9nm+tEwBAn2bszr1fQID4f2I3-vUv38uJSX4b3FdxZUaEEkMGX8BJqW2HfE2ycN4A2mq-ZAltVhOGXosWSv8HL6y8ksNgC9OgvwBEg5ybAmBuRfklHu2ojLANMqAjS-8r7fmPmFNIsVMibFIXAohqUB7vwcJlPI-IaDjAWAkbWbR8IwMChXeGKwNT0HorbcKcUEqsKyhXARKwKFSPKKfKMtcqQ10ETgverxeATSWCYw2hiYHGLUcgtu2oRjULmMIg4lJZEuNNkYpxmjbrOJAbgrxIiPif00YxFBhFb78hCaRPODAXE-3CbAtxAk85RPidRJxsSMRJNCdo7J0SkmMNQUDJxujnLmLwg1VR3AWQpIXByEeUgx5dWFH1KeKE6yNwKTIoMwUG4ZLkUfHp0Cin1gyQkXO9AAyFyVqXXs3ccwCKTjE6QadzxNJVrHQI8dVoF3AjXeG4dOzo39psma-COAllGLwA5LZvasxgleU5iSbH0ObvIqxTjCFZJsR9fxFcvnV0rnsDxHz-lGQ7nnN5hSEnGK+UfKBvzPFgp3pA000Ks7-0SC7ZOq1mQuyLo0h5XUjpoBOiEAArmgMQlKoAgDUAAG3pRiv6oxsVSSaHEfFMzo4xhJSdSK1KpR0sZcyj+UA2WMEGOK643KrwABU1BKDEGEGUEAACetKGVMsdgka4SQrR5yICs4YYjCXHO2rtfafLYqUpRMAXw4AID6CAA

  Are you sure? yes | no

Similar Projects

A data storage solution based on PAL-delaylines
Project Owner Contributor

Delayline Memory

tobias-fricketobias fricke

Arithmetic Logic Unit
Project Owner Contributor

ALU

lilia-lobatoLilia Lobato

a 16-bits YASEP computer (mostly) made of DIP/SOIC chips like in the 70s and 80s... with 2010's twists!
Project Owner Contributor

Discrete YASEP

yann-guidon-ygdesYann Guidon / YGDES

Uploading / downloading Intel HEX file stream during system runtime, implemented without embedded processor!
Project Owner Contributor

Intel HEX files for FPGAs (no embedded CPUs!)

zpekiczpekic

Does this project spark your interest?

Become a member to follow this project and never miss any updates

Going up?

About Us Contact Hackaday.io Give Feedback Terms of Use Privacy Policy Hackaday API

© 2026 Hackaday

Yes, delete it Cancel

Report project as inappropriate

You are about to report the project "DTAP2-ULSR", please tell us the reason.

Send message

Your application has been submitted.

Remove Member

Are you sure you want to remove yourself as a member for this project?

Project owner will be notified upon removal.