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• Debug with 3 Alien Probes

  Jacques Pelletier • 4 天前 • 0 comments

  With a 3rd Alien Probe (Generic), I probed additional signals routed to the 6116 RAM and the 2 bus buffers enable.

  It looks like the bit bucket is working properly.

  LDZSYS now runs without complaining, but DIAG still doesn't work.

• EPROM address lines bug

  Jacques Pelletier • 05/31/2026 at 12:37 • 0 comments

  The 2 EPROM chips are connected to address LA0 to LA10 instead of LA1 to LA11 so I double the bytes instead of an ugly hardware patch. I use the 2 files BOOTEVEN and BOOTODD, but I doubled every bytes.
  Still with this modification, the DIAG utility doesn't work.

• Flip-flop modifications

  Jacques Pelletier • 05/31/2026 at 11:30 • 0 comments

  I made the modifications of the flip-flop logic and it seems to work. The diag utility goes further but the BBTC still doesn't work yet.

• Debugged the NMI flip flop logic

  Jacques Pelletier • 05/30/2026 at 16:59 • 0 comments

  With the help of my Alien Probes, I found out that the NMI flip flop remains set when activated and a reset signal couldn't reset the chip. 

  So the circuit in the CPLD doesn't work as expected. With TTL logic, the circuit works.

  I made a small modification in the CLPD to check only the NMI flip flop logic, and it works now.

• Debugging with the Z8001 Alien Probe

  Jacques Pelletier • 05/22/2026 at 18:21 • 0 comments

  The Alien probe was useful for checking the wiring and memories. Memories are working fine. Next step is to check the bit bucket with both the Z8001 and PC XT Alien Probes.

• BBTC Project slowed down

  Jacques Pelletier • 01/24/2026 at 04:59 • 0 comments

  Last year, I had a lot of free time until late autumn. I returned to work in November, so my projects will slow down.

  The possible next steps:

  implement the Trump card with discrete logic to see if it works with the software

  making a simulator to run Z8000 code on Linux

  port this simulator to run in the Z8001 alien probe

  add a UART in the CPLD to help debugging or

  add an interceptor socket with which I can add peripherals to the current BBTC

  there is already a disassembler for the Z8000 running on Linux

• Debugging the CPLD: 5

  Jacques Pelletier • 01/05/2026 at 04:46 • 0 comments

  I figured which chip goes where. I combined the 2 binary files and disassembled the result. I tried a disassembly of the swapped file but it was obviously not good so I scrapped it. I added the files in this project.

  Command to combine the 2 binary files:

  srec_cat -o BOOT.bin -binary BOOTODD -binary -unsplit 2 0 BOOTEVEN -binary -unsplit 2 1 

   Location of boot chips:

  D8-15: BOOTEVEN

  U7 on BBTC, U21 on TC

  D0-7: BOOTODD

  U8 on BBTC, U22 on TC

  The listing in the original article seems to be an old version. The 2 files on the software disk are a derivative.

• Debugging the CPLD: 4

  Jacques Pelletier • 01/04/2026 at 11:03 • 0 comments

  I tried swapping the 2 boot chips, same result. Removed both, same result.
  At this point, I need to know:
  Do the files BOOTEVEN and BOOTODD match the original Trump Card boot chips and which goes where (D0-7/D8-15)?
  I reproduced the circuit from the article except for the dynamic RAM. I know there was an error in the DRAM logic but that didn't affect my version. I don't know if there are difference between the schematic and the official Trump Card.
  If someone have a working Trump Card, I would like to see the result of the DIAG.COM program.
  

• Debugging the CPLD: 3

  Jacques Pelletier • 01/03/2026 at 04:05 • 0 comments

  The initialization sequence in the article seems to be incomplete. I used the files BOOTEVEN and BOOTODD provided on the Trump Card's floppy disk.

  LDZSYS doesn't load either, but using diag.exe, I can test the bucket circuit further this time.

• Debugging the CPLD: 2

  Jacques Pelletier • 01/02/2026 at 20:25 • 0 comments

  I used my PC XT alien probe to check every control lines, data and address bus.
  The CPLD was mysteriously keeping address A0 stuck at 0. 

  There was no short with ground, so I added an inverter on A0 in the CPLD with the output going to an unused pin. There was no need to make any patch on the PCB (yet).

  With the pin A0 configured as an input, it was no longer hanging the bus and I could plug the BBTC on the PC XT motherboard. 

  However, the BBTC still didn't work. LDZSYS was not able to connect to the Z8001, and the DIAG program remained stuck.

  The bucket simulation seems to work OK.

  The listing of the bootstrap initialization program doesn't match the files BOOTODD and BOOTEVEN.

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