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• Second PCB version ordered

  roelh • 10/19/2024 at 08:49 • 1 comment

  Yesterday I finally ordered the new PCB. This PCB is sponsored by the kind people of PCBWay, the well-known high-quality PCB fabrication company from China. During production you can always check in which production state your pcb is, and I watched an impressive series of videos that show all steps in the production process.

  This is the KiCad 3D-impression of the new PCB:

  With respect to the first PCB, the main changes are:

   - fix mistakes (VGA connector)
   - add Mouse connector
   - add HW for sending info to keyboard (and mouse)
   - add memory bank select
   - change video pixel/color generation for 640x400 mode
   - change WiFi module type
   - simple 4-wire connect to Raspberry Pi (for file transfer)
   - instead of a SPI header, a micro-SD card connector is mounted
   - changed SPI reading, it can now be done in 2 cycles/bit (instead of 5)

• Changed bankswitching system

  roelh • 10/14/2024 at 12:59 • 0 comments

  In this previous log I described the new bankswitching system. But I wanted to add another mode (Linear mode). It would be nice if a program could access the whole 512kB memory without bankswitching. The address would be in a 3-byte register, with 19 significant address bits. A simple processor with 19-bit addresses could then be implemented.

  For programming the Z80 or 6502, it is not needed to know all this. You only need this if you implement a bankswitching system or a new processor microcode that accesses the whole memory. Probably it is only for myself.

  I came up with the following: (All images can be enlarged by clicking them)

  LINEAR MODE

  The functions are essentially the same as in the mentioned previous log, but I added the Linear mode. For program code, the upper bits A18 and A17 come from a bank select register, and A16 comes from microcode. For data, upper bits A18, A17 and A16 come from another bank select register. So, the upper three address bits can be different for program and data. Also new is, that this bank select register can be loaded from a memory-resident register in a single cycle.

  APPLICATION and KERNEL

  It is intended that, for Application and Kernel modes, BS_2 and PC18 are always written with the same value. That makes our table slightly less complex:

  This diagram shows all modes. The modes are controlled by signals in the microcode and the bank select registers, as shown.
  

  HARDWARE IMPLEMENTATION

  The result is a bit complex because I didn't want to add more chips. Another complication is, that the address must be available quite fast, so there can not be long propagation delays. The following diagrams (there are seven) explain all modes, and also the way it is implemented. The used colors are the same as in the table above.

  You find the bankswitching control registers at the top of the diagram. The microcode control signals are at the left side. At the right side, you find the five highest address bits, their value indicated by '0' or a color.
  

  REGISTER MODE

  This is the simplest. The (memory resident) registers are in the very first 256 bytes of memory. This mode is selected by CTL_M1 = 1. The CTL_M1 signal switches all upper address outputs OFF, so all upper address bits are zero. The register in question is selected by several bits in the microcode.
  

  The value in the bank select registers is irrelevant.

  TABLE / ZPAGE

  In this mode only the lower 8 bits of a data or code address are used. The other bits are zero, but A16 and A17 come from microcode. It is used for 6502 Z-page, for an identity table and a shift-right table. If A16=0 and A17=0, this mode can not be used (that is the domain of the memory-resident registers).
  

  This mode is selected by microcode signals only. The value in the bank select registers is irrelevant.
  

  NATIVE

  This is the main addressing mode of the first prototype. The upper address bits are 'hardwired' in the microcode. Bit A18 can no longer be used, that should not be a big problem because this will no longer be the main addressing mode.
  

  This mode is selected by microcode signals only. The value in the bank select registers is irrelevant.
  

  APPLICATION MODE

  Here, the upper three address bits are freely programmable in the bank select register U50. It is advisable to set BS_2 equal to PC18, otherwise the topmost address bit is different for code and data (also for the following two modes kernel slot1/slot3).
  

  This mode is selected by microcode signals in combination with APPL = 1. Yes, the APPL signal got it's name from this mode.
  

  KERNEL SLOT1

  The 64k addressing range is split up in four slots:
  

  • Slot 0 ( 0000 - 3FFF )
  • Slot 1  (4000 - 7FFF)
  • Slot 2 (8000 - BFFF)
  • Slot 3 (C000 - FFFF)

  In this kernel-slot1 mode, normally the microcode selects which 64k bank is selected (orange signals). But if the address is in slot 1, the bank number comes from the bank select register (light...

  Read more »

• Fixing the LDIR instruction

  roelh • 09/17/2024 at 20:18 • 0 comments

  In the past weeks, I've been working on a new pcb design. That's now almost done.

  This weekend I looked at my TODO list, and I found, no surprise, the LDIR instruction.

  In one of the previous logs I mentioned that there was an error in the LDIR instruction. It didn't behave correctly when an interrupt occurred.

  What is the LDIR instruction ? 

  In the Z80 processor, this instruction can copy a whole section of memory in just a single instruction. It takes three 16-bit sized values as input:
   - A source address in register pair HL
   - A destination address in register pair DE
   - A byte count in register pair BC

  LDIR stands for Load, Increment, Repeat.

  
  It will do the following actions:
   - read a byte from the address at location HL
   - write that byte at location DE
   - increment the addresses in HL and DE
   - decrement the byte counter in BC
   - if the byte counter is not zero, repeat the actions
   - if an interrupt occurs during this instruction, it will be handled and the actions will continue after interrupt is handled.

  LDIR has a 2-byte opcode: ED B0

  Optimizing the LDIR

  The LDIR was already optimized, with 10 cycles per copied byte, but I had the strong feeling that something better was possible. I didn't try to find the problem in the old version, just started again from scratch.
  

  Isetta has only a single hardware data pointer. But nothing keeps us from using the program counter as a data pointer ! For a normal instruction, that would cost way too many cycles, but for a repeated transfer instruction this will pay off. The LDIR microcode should just save the PC to a temporary location, and copy the HL register pair into the PC. Now the PC can be used to get the bytes out of memory. When all actions are completed, the PC is copied back to HL, and PC is restored from the temporary location. The existing, broken LDIR version also had this feature.
  And as a bonus, the PC register can increment in the same cycle where it addresses a byte to be fetched.
  
  

  The destination pointer (register pair D E) is copied to the hardware registers DPH and DPL. The byte, fetched with the address in PC, can now be stored at the address in DPH/DPL. There is a microinstruction that increments DPL, it can also detect a carry, but there is no possibility to increment the DPH register, because it can not be accessed after the change that is described HERE. But we could increment the D register and re-write DPH with the result. This will at least take 3 more cycles (microinstructions).

  Then we must decrement the count in the BC registers. So first decrement C (2 cycles) and, when it drops below zero, decrement B (also 2 cycles). 

  The problems are in the counting, and in the increment of the upper byte (DPH), 

  But if we unroll the loop, in sections of 8 transfers, we don't have to count each byte. We simply subtract 8 from the LSB of the count, at the beginning of the unrolled loop. But when the count is lower than 8, we jump to a slow old-fashioned loop. This will decrement the MSB of the count when that is needed, and then go back to the unrolled loop. The slow loop will also check for zero to determine if the instruction has completed.

  It would be nice if we never had to increment the upper byte (DPH)...  What if we never increment the upper byte in the unrolled loop ? Before the unrolled loop starts, we could check if the lower byte (DPL) would overflow in that loop. That would happen if that lower byte is higher than 0xF7 (247), and in that case we do the old-fashioned loop, and when the upper byte has been incremented, we go to the unrolled loop again.

  Now, the sections of the unrolled loop have only 3 cycles:
   - A <- (PC++)
   - (DPH/DPL) <- A
   - inc DPL

  Pseudo code of the fast copy loop:
   - if LSB of the count < 8, goto slow loop
   - if LSB of destination > 247, goto slow loop
   - count = count - 8
   - copy the DE registers (destination)...

  Read more »

• Progress of new PCB

  roelh • 09/07/2024 at 10:14 • 0 comments

  Here is an impression of the new PCB (Image generated by KiCad). It's almost finished.

  And here is a small section (of four IC's) :

  The TOP layer is RED, first inner layer is groundplane (not shown), second inner layer is ORANGE and the BOTTOM layer is BLUE. You can click on the picture for a better view.

  Yes, all routed by hand.

• On the cover of the hack a day

  roelh • 08/31/2024 at 18:12 • 5 comments

  The Isetta made it to the front page !

  The Computer We All Wish We’d Had In The 8-Bit Era by Jenny List.
  

  We take all kind of pills
  That give us all kind of thrills
  But only one thrill is gonna stay 
  Thats the thrill that you'll get when you find your project
  On the cover of the hack a day

  
  (Hack a Day) Wanna see my project on the cover
  (Day) Made a big printout just for my mother (yeah)
  (Day) Wanna see my smilin' face
  When my project is on Hack a Day

  Thank you, Jenny !

  Understand a little Dutch ? We've got you covered. There is a nice cover of the cover....

• Hardware changes and bankswitching

  roelh • 07/28/2024 at 15:30 • 0 comments

  Luckily, the first prototype worked without real problems. The only obvious one being the strange footprint for the VGA connector. 

  But for my next pcb run, I want to do several changes:

   - fix mistakes (VGA connector)
   - add Mouse connector
   - add HW for sending info to keyboard (and mouse)
   - add memory bank select
   - change video pixel/color generation
   - change WiFi module type
   - simple 4-wire connect to Raspberry Pi (file transfer)

  BANKSWITCHING

  The memory bank selection is, I think, the most complicated of this new features. The new system will have the following modes: Register, Table/ZPage, Native, Application, Kernel slot1, and Kernel slot3. You can see that in the following table:

  In the current hardware, only the Register mode, Table/ZPage and Native mode are present. The register mode allows access to 64 fixed locations in memory (a kind of zero-page addressing). There is another group of 64 locations that can be switched (for Z80 registerbank switching). Table/ZPage mode is used with an identity (1:1) table to access DPL and PCL, to access the Shift-right table, and for the 6502 to address ZPage values. The Native mode allows addressing the full 512 Kbyte of memory, but it's problem is, that the used 64K bank (yellow fields) is hard programmed in the microcode.

  This will now be more flexible. In the new Application mode, one of the 8 selectable 64K banks can be programmed in a bank select register (blue fields). The selected bank will be valid for data as well as program code. Note that the microcode can force that Native mode or Register mode is used, by using the control bits CTL_M1 or CTL_REG2.

  An operating system must be able to access all memory, to be able to load programs and move data around. I want to adhere to a common practice in several Z80 systems, where the memory space is divided in slots of 16Kbyte. To make this not too complicated, only 2 of these 16Kbyte slots can be mapped to another 64k memory bank.

  So, the Kernel_slot1 mode allows you to map any of the 32 blocks of 16kByte into slot 1 . Eight banks of 64K can be chosen with the blue BS signals, while within such a 64K bank, a 16K block can be chosen with the orange BLK signals. Slot0, 2 and 3 will select the 64K bank that is defined in the microcode instruction (with the yellow BNK signals).

  The Kernel_slot3 mode allows you to map another block in slot3. But this has a few restrictions. The mapped-in block can be any 64K bank, but within that bank it is always block3. And no code can be executed from the mapped-in block.

  In the table, the bits indicated in RED show which bits are needed to select a certain mode. For the bank select register, there are only 3 types: Application/Native, Kernel_slot1 and Kernel_slot3.

  VIDEO CHANGE

  In the current video system, in the 640-pixel mode, a byte from memory represents 8 pixels, and the byte tells for each pixel if it has foreground color or background color.

  But this system was designed when the processor/memory cycle was still 160nS.

  Now that I changed the cycle time to 80 nS some time ago, a fetched byte only needs to provide color for two pixels (pixels last 40nS). So we can simply have 4 bits (16 colors) per pixel ! Now each pixel can have an independent color.  This seems much more flexible than the previous system, so I'm gonna change that. 

  VGA connector footprint issue

  It turnes out that all KiCad footprints for these DSUB-15HD connectors are wrong, and that was known already 5 years ago, see this issue report. Swiching to the newest 8.0 version still had the wrong footprint. So I had to edit the footprint myself.
  

• Two Spectrum games working

  roelh • 06/27/2024 at 20:39 • 0 comments

  After a little while, I got the Manic Miner fully working, including sound:

  But in the video signal, there are two annoying stripes at the right side of the screen (also going through the score). This is related to a end-of-line flag that is tested there in the microcode that builds the screen. The exact reason is not known yet. [ edit: the reason was found, and the bug removed.]

  SOUND

  The sound took a little fiddling to get it to work properly. The ZX Spectrum has a very simple sound system, similar to that of the Apple II. It is a single bit of an output port (port 0xFE), that is amplified with a single transistor, and connected to a small speaker. The program has loops that toggle that bit with a certain timing.

  The Z80 of the Spectrum runs at 3.5 MHz. Isetta runs at 12.5 MHz. But Isetta spends around 73% of her time rendering the Spectrum screen, so her effective speed is about 3.375 MHz. A Spectrum program, generating a constant tone, would come out as a series of high-frequency 'chirps' during blanking time.

  The write to the 0xFE output port is handled by microcode. It now stores the value instead of writing it to the speaker. At every line interrupt, this value is put in a buffer (only during blanking time when the Z80 code runs, that is about 140 lines per frame ). But in every line interrupt (525 times per frame), a value is read from the buffer and written to the sound output. The same value is used four times, and then the buffer pointer is incremented. So the sound is stretched by a factor 4.

  It had another problem. The sound bit is normally zero, then it toggles during the tone, and then is zero again. This means that it has a low-frequency component. In the ZX with its tiny speaker this was probably no problem, but in my case I have a set of amplified PC-speakers (with 3.5 mm jack connector) that have a 'good' bass response. So the little 'music' tones were accompanied by loud plop sounds.

  The sound system of Isetta has 8-bit samples. I defined a level that was halfway the 0 and 1 of the speaker signal. So normally the signal was at 50%. When port 0xFE was written, the signal would be 0% or 100 %. But the point is, it is difficult to know when the tone stops, so you don't know when to go back to 50% . I did this as follows. At each interrupt, when the 0xEF port was not written, I bring the speaker signal a few steps closer to 50%. So when the tone stops, the signal will go to 50% quite soon. This gave a reasonable sound quality.

  KEYBOARD

  I already had Z80 code to convert the PS/2 keyboard to ASCII, and to convert ASCII to the codes for the ZX Spectrum keyboard matrix. But for playing a game, I also had to use the PS/2 'key released' messages, to tell the game program exactly when a key was released. 

  THE GREAT ESCAPE

  I tried another program. The Great Escape. This program also has a very good, commented disassembly. 

  In this program, a prisoner of war has to escape from a prisoners camp. It is totally different from the previous game.

  The display is a semi-3D rendering. It is almost a modern game, where a camera follows the hero on the terrain and in the several buildings.

  It did not take much time before I saw the first guards walking on the screen. But it was only a few second, then the program crashed. What could it be ? I looked through the source and I found it used an instruction that I had not implemented, because my thought had been, who is ever going to use that ??  RRD  Rotate Right Digit

  But the game uses it to shift the whole screen four pixels to the left or the right....

  So the RRD and RLD are now also in the microcode.

  Program worked. But I have no clue how to escape...

  [ edit: What David Thomas says about the great escape ]

• Trying to get a ZX Spectrum game running

  roelh • 06/14/2024 at 14:44 • 0 comments

  TEXT MODE

  In the last log I mentioned that there was video output.

  A 80-column text mode was created. Each character is in a 8 x 8 pixel matrix. To make it better readable, a few empty scanlines are between the textlines. The VGA pixels are generated by the microcode.

  At the moment this is mainly used as a text mode, although it is actually a graphic mode with 8 bytes of 8 pixels each. For each row of a 'character', there is also a color byte. The idea is that every character can have a different color (but since this is a graphic mode, each row of a character could have it's own color). The background color for a character can also change, but that's not fully implemented yet.

  The picture shows how the system starts in the current version. It shows a few big colored fields to show some of the colors. At the right side you see some random colors, where you can see that each character can have a different color for each row.

  You also see how the file directory shows up. A line that starts with "D" means that this is a directory.

  After I got this video mode working, I worked on the PS/2 keyboard input. The keyboard did only give a singe message after startup, always the same, and did not respond to key presses. After searching my keyboard on the internet, I found that some keyboards need a RESET message before they start working. In my case, I had to solder two transistors on the pcb to be able to transmit the reset message to the keyboard. But then it worked ! A Z80 program translates the scancodes to ASCII. 

  Isetta can now run with its own keyboard, video output and file system, without the need for the RPi !

  ZX Spectrum video system

  After I got that working, I spend some time making a video mode that behaves as ZX Spectrum graphics .

  To test this, I downloaded the source of the game Manic Miner. I could only get this to work if I also found the explanation of Manic Miner source code. Here is the first result:

  Obviously, not everything was working correctly yet. There were vertical lines at every character boundary, and apparently the attribute bytes of the lower part of the screen were not correct.

  It could be traced (within reasonable time) to a failing LDIR (load-increment-repeat) instruction. This is used in the game to copy big blocks of bytes to the screen, with a single instruction. The LDIR, that is implemented in microcode, was designed to check for an interrupt periodically, and in the case of interrupt set the program counter two steps back, and after the interrupt resume the copy operation. But it didn't work correctly with interrupts.

  The LDIR was a highly optimized piece of microcode. At ten cycles per transferred byte, it loaded the byte, stored it at the destination, incremented the HL source address (with carry between low and high byte), do the same for the DE destination address, decrement the BC byte counter, test if BC is zero. And also check the interrupt signal at every transferred byte.

  I took the fast way out. I grabbed a RST instruction (0x20) and did put a copy routine there. In the source of the Manic Miner, I replaced every LDIR with a RST 0x20. Followed by a NOP to leave addresses unchanged. Getting the bug out of the LDIR instruction was put on the TODO list. Now I got this:

  Already much better !

  I could also see on the piano keys that the start-up tune was playing (but of course I have no sound yet). Also, a scrolling message was visible. After that, the program crashed. More debugging to do !

• Who is afraid of Red, Green and Blue ?

  roelh • 05/15/2024 at 20:17 • 0 comments

  A true milestone today !  Just half an hour ago...

  The picture shows my test setup, with a laptop, scope, Raspberry-Pi screen, and....

  FIRST VIDEO OUTPUT !

  It shows just a simple testpattern that I quickly made up. Colored bars and pixel patterns, and when I wrote it I had no idea how it would look. I did not bother to start the pixels at the correct distance from the sync pulse, so apparently I started much too soon since a the right-side, one-third of the screen is empty. (but I also just generated 60 characters instead of 80, to have simpler code).

  The picture gets its stability from the timer interrupt on Isetta. The picture stays fully stable if I give Isetta commands via the Raspberry Pi screen. On the Isetta, there is no need for forcing your code in certain blocks with exact equal amount of cycles as in some other designs. (but of course, the interrupt code that generates the picture must have exact timing).

  You can see on the picture that the video connector connects with wires to the pcb. That's because I used the wrong footprint for the 15 pin video connector. I had no idea that there were different types. The difference seems to be that one has a row distance of 2 mm and the other one a distance of 2.5 (or 2.54) mm.

  Soon there will be characters on the screen !

• File system and command shell

  roelh • 05/14/2024 at 20:38 • 0 comments

  FILE SYSTEM

  Isetta has a 32MByte serial flash, and it is there because I want her to have a file system.

  While making this file system, I also make a simple command shell, at first just for testing the file system functions but it will grow to get every command that is needed.

  The serial flash is a W25Q256JV device. It has 8,192 erasable sectors of 4kByte each.

  It would be cool to have a little wear-leveling. That almost rules out a FAT system, where an allocation table is written to the same sector, each time as one of the files changes (unless you write it on a different position each time).

  What did I come up with ? The system has the following properties:
   - files (that consist of one or more sectors)
   - hierarchical directory structure
   - deleted or overwritten files stay available (but are normally not visible in the directory), until erased (after adjustable time).
   - supports hidden files

  FILE STRUCTURE

  The first sector of a file (or directory) has this structure:
  At 0x0000:
   - (byte) flags
   - (word) sector of the directory that it belongs to
   - (byte) lsb of the properties address
   - (byte) hash of the name
   - (byte sequence) name (zero-terminated), max ca 100 chars.
  At properties:
   - (word) number of the following sector
   - (word) reserved for more flags (unused yet)
   - (4 bytes) date (YYYYMMDD, so today is 20 24 05 14)
   - (4 bytes) time (HHMMSS00) (so it is zero-terminated).
   - (4 bytes) file size (little-endian)

  At 0x0100:
   - maximal 0x0F00 bytes of data 

  The first sector has a lot of space to define more properties. For the sectors that follow, only the flags and the number of the next following sector need to be present. For ease of programming, the data in these following sectors also start at 0x0100.

  The flags at address 0 are these ( they are active low ):
   - bit0  if 0, sector is ready to be written
   - bit1  if 0, sector is in use
   - bit2  if 0, sector belongs to a file (but is not first sector)
   - bit3  if 0, this is a directory
   - bit4  if 0, this file was deleted (but still available)
   - bit5  unused
   - bit6  unused
   - bit7  if 0, this file is hidden

  FLASH LAYOUT

  Where are the files placed in the flash and how do we find them back ?
  There are two rules:
    - The first sector of a file will be placed at a position that is based on  the directory that it belongs to, and on a hash function of it's name. If that position is occupied, it will start looking for an empty position in one of the following sectors.
    - The following sectors of a file can be placed anywhere, since they are all linked.

  There is only one fixed position, and that is the ROOT directory at sector 1.

  DIRECTORIES

  The flash is divided in 8 compartments. The files of a certain directory will all be stored in the same compartment. A simple hash function, applied to the sector number of the directory, tells with compartment it belongs to.

  FILES

  In every compartment there are 1024 sectors. A hash function, calculated from the first and last character of the file name, determines the preferred position of the first sector in the compartment. If the preferred position is already occupied, the first free sector that follows this preferred position will be used. 

  So, when the file name is known, it can be found very fast, because only the flags, directory, and name of a file have to be checked in each sector. In most cases it is not needed to check the full filename, because checking the hash is sufficient. In such cases only 5 bytes of the sector need to be read.

  When the file name is not known (when asking a directory) only a single compartment has to be searched for valid files. Only the flags and the directory sector have to be checked. This is also very fast, when you type a "ls" command you don't notice any delay.

  The bytes for date and time have the highest bit...

  Read more »

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