I've done a "quick" (a.k.a. 60 minute) model of 3 more components. 

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The sprocket now has 3d modelled "teeth" that I took inspiration from searching "ball chain" on thingiverse.

I've modelled it such that the diametric magnet is held inside. This hopefully makes it much easier to center on the motor.

I had to move the motor down a bit so that the minimum wall thickness of the pulley I like how the PCB coincidentally matches the edge of the chain path. I also like how simple this all looks, even though it's taken months on and off to get here.

Then there's the start of the slider mount, as well as the pulley. There probably should be some kind of LCD wire cutout somewhere on it. This also might be the thing that holds the pulley, but since I haven't yet figured out a way of mounting the BLDC + PCB as a self-enclosed unit (hence, the mounting geometry would have to be created in Tetent/Leti instead of just worrying about mounting screws and clearance like the first Tetrinsic concept), I'm not in any urgency to compute a solution. Ideally, the tubes snap into place in the little trenches for them:

The pulley itself is a 3mm dowel + 2 needle roller bearings used in BMG extruders for FDM 3D printers + 5mm inner, 7mm outer tube. The tube material is either silicone or PTFE, though silicone is slightly cheaper.

 The reason I'm not using a metal bearing material because I want to dampen noise and any vibrations that may occur.

I think I might finally now have enough stuff conceptualised to actually create a proof-of-concept device, thought I'd have to make a USBC-to-24pin adapter / development board first. For Tetrinsic itself, the BOM so far looks like this:

The price difference between the total and the per-each price is because some components, like the magnets, can only be bought in quantities exceeding what I need. As I expected, it was going to be around £250 for 10pcs. Not great, not terrible, but that's £200 per Tetent. Also note that this doesn't include costs for the solar cell version, though I'd imagine it'll be similar to the price of the 1.47" display.

The proof-of-concept would just have a 3D printed slider surface in the place of the LCD / solar cell.

So you might be wondering why everything looks completely different now.

Electronics

Well it started when I deleted the regular weight of Essence Sans specifically so that Fusion 360 would give me the bold version:

Then I realised that, from the front of the LCD, the pinout is 12 - 1 not 1 - 12:

I wasn't going to be fixing that, so instead I thought of another idea, which is flipping the motor-PCB sandwich around:

It was a good strat which could eliminate the need for the extension cable, until I realised that there wouldn't be a way for the ball-chain to reach the pulley.

New orientation ideas

I then started looking into some new orientation ideas, since I made the PCB smaller than expected, as well as self-contained:

This was really an attempt to reduce the size of Tetrinsic, but it wasn't working so I thought that I should increase the sliding area : footprint ratio.

Well I saw this and thought that if I had space to do this, I had space for the ball-chain to just go around the motor entirely.

The above is my first idea, where the ball chain will slide to the side of the load cell. The below is an idea to get around the mounting screws such that I could still connect multiple Tetrinsics in a row on a printed bar, but the bends were too shallow. 

This was also the moment that I upgraded to 3.2mm balls, since that's the smallest that has a splicing tool, and I'm thinking that the larger the ball, the easier it may be to actually do the splice manually / with a 3D printed tool. 

I started making some 1.5mm stainless steel bends:

Then I was making the chain pathway.

The above didn't look right, so I made a helix, projected it and I think I got a good approximation from a 3 point spline:

Lastly, I added some Jointables (surfaces I use to joint this component to others in other files) and imported it into the Tetent file. 

I've barely got any space left if I don't want to make #Teti [gd0022] larger.

The active area of Tetrinsic is now 48mm, up from 32mm. It's likely that I'd have to loop the steel wire under, like what I've done on the motor side. In that event, the active area will be 52mm and the footprint length will be 3mm longer.

So I noticed that one of the components were rotated the wrong way:

I thought "I would've been able to see and avoid this problem if I could actually see where the pads were.

Seems that was the only issue, but I thought I should look into this silkscreen issue.

The actual silkscreen is a mess...

...so I thought of making a new layer entirely:

I moved my rectangle to the new layer and tried to set up the postprocessor, but it doesn't seem to have worked:

It also wasn't showing correctly in the CAM preview.

I then found this in the Layer Sets Manager, and I removed tPlace and tNames and added OverSilk. The preview now looks as intended, at least.

Still doesn't look correct on JLC's site though.

Now that was effort. It was mostly straightforward, but there were vias inbetween passive pads that would no longer fit. I had to move the AAT101 down 0.4mm to make the available space. It shouldn't affect the Tetrinsic CAD model all too much.

I also had to tap into the GNDPlane for 2 more signals. Still, the pour coverage seems good.

It seems that 5 boards are £1.72, 10 boards are £5.50 and 15 boards has some £19 engineering setup fee. I think I remember seeing something about the SMT service having a limit of 50*50mm, so perhaps I should actually panelise 4 into one larger board. The image above is for 10 boards, of which 2 would be spare.

When everything is in the checkout, along with the coupon, and using the cheapest shipping method:

Fedex, the next fastest delivery option, increases the total to £25.

So I was on JLCPCB, looking uploading the GERBER files to see the PCB price, and I saw something:

So if I can get 5 boards pre-assembled without the processing fee, I was wondering if I should go down that option. I looked for the ICs on the top of the board, and while they existed, they were much more expensive than on Digikey/Aliexpress.

Then I got the idea that, since there's only 5 ICs total and that's where the bulk of the PCB cost is anyway, I could get the SMT service to only place the long list of passives. I soon realised that a stencil wouldn't work after components are already on it, but I remembered a project on Hackaday giving tips and tricks to high density PCB assembly and this log had a strategy that could work without the need for a stencil.

So I went into the Fusion 360 CAM Processor and I exported the BOM and Pick And Place files to CSV. Then I deleted the components I didn't need and formatted the tables like the example files provided. Fusion exports positional data just as numbers, but I found out that I can set up custom formatting in Excel. This is what I used in the 'Type:' box:

0.00"mm"

That is a number with 2 decimal places and "mm" after it, just like in the example file. 

So the components actually imported and I just picked one of the first 5 options for the NPN in the "basic parts" list that had a low price and a high dissipation and sink current (all relatively speaking against the other 4 options):

I think the backlight of the 1.47" screen takes 180mA, so I thought the cheapest part on the list was going to cut it close:

Hopefully, I can name it in the schematic and it will be automatically found in the future:

The real issue was the bulk capacitor. The 22uF capacitor for the +3.3V supply was fine, but 6.3V wouldn't be high enough for a 12V +VBLDC rail. I looked in my PCB and Me In The Past luckily designed it such that I had more space available for capacitors that I hadn't used.

So how much capacitance do I actually need, anyway? Well I don't know, couldn't really find anything on the internet, and the datasheet seems to be avoiding the question: 

Oh wait. I didn't see that last line before the image when I was researching all this It says the capacitance right here:

Doesn't matter because, after looking through my options and finding out a 1206 was much too large...

... I found a suitable 0603:

So, assuming that the more bulk capacitance the better, I go in and start stacking capacitors in the schematic like magic circles seen in powerful incantations and then I pushpull my way to a solution:

and I'm thinking "could I even get a 4th bulk capacitor in here? Wait, isn't that bottom via used for grounding the corner GND pad?"

Yes, I had 2 ground vias right next to each other.

These bulk capacitors were slightly closer to each other than any other array of passives on the board, and I really wasn't liking the idea of 3.3V merely 0.25mm away from higher voltages. It took another 10 minutes, but I was able to space everything out, remembering to make sure that the the electrons go through +3.3V pads:

Now I'm cleaning up traces before uploading to JLCPCB again.

So, with some slight tweaks to the names of components, the automatic BOM generator worked. It also seems that all of them are charged at a minimum rate of 20pcs, and since only 2 components exceds that, it's certainly better to have them assemble 5pcs than 2pcs.

This is what my preview looks like:

I think Fusion 360 was lazy with the silkscreen generation and it's just covered the pads. Still though, thats a lot of components that I may no long have to source and tediously place by hand if I can get the no-stencil method to work.

I'm wondering if I should let JLC figure something out on this tiny board or if I should add some tabs on the top / bottom that include these holes. Additionally, while it costs an extra 35p for each of these 2 confirmations, I think it's a good idea since these are 1st gen prototype boards.

Something also intersting is that I can have the SMT service or a stencil, but not both. I hope I can do that non-stencil method on the large ESP32-S3-MINI on the back.

So, even with the 70p confirmation fees and the £6.29 setup fee that I should be able to redeem a coupon for, 5 assembled PCBs cost less than £11. That means I could theoretically spend as low as £3.80. The components and SMT assembly only cost a mere £1.05! That's 21p a board!

Wait... I forgot to enable settings for the board itself.

That sounds expensive. it kinda seems that I could still have my 0.4 outer diameter vias though. It also seems that there's a price bump when I opt for a 0.8mm thick PCB as opposed to 1mm and up. I'm not that critical of 0.2mm. Anyway, I've got to go in and change the minimum via holes to 0.3mm. Most of them are converting, but there are some that dont'.

I've seemingly spent 3+ combined hours just tweaking traces and making them look nicer:

I thickened traces like the +3.3V line, as well as tweak traces like POSITIOIN so that it looked tangential to the "e" in "Tetrinsic":

The most notable thing I've done probably is finding a way to route all the I2S pins without a via in the pad:

I believe having a via in a large ground pad that is exposed is much better than in a small signal pad that is hidden:

Now I'm researching the USB implementation of the S3. Basically, I just want to make sure that I can flash the board without the TX/RX pins (which looks to be the case) and that I don't get strange behaviour on the ADC, of which many pins used are also used for some "external PHY" feature:

What it sounds like is that I might have to burn an efuse, but also that I might not have to since it's software configurable which USB interface is connected:

I actually thought USB was one single feature, but it's actually 2 different ones. It seems that the OTG mode allows the chip to act as both a USB host or a device, which I didn't know microcontrollers could do (note that it wasn't until late last year that I found out there were microcontrollers with native USB in the first place). 

Oh and I've just realised this bypass capacitor is in the wrong location to actually do any filtering for the AAT101:

Why do I need that again?

Right ok so bullet point 1 is what that bypass was supposed to do, bullet 2 are those 6 passives on the way to the ADC and the ADC itself does bullet 3. Ok... I better get a reaaaaly clean signal after I spend all the time to cram this final capacitor in...

... and I'm done. 

Adding the capacitor in took like 6 minutes thanks to the power of autopush. I then spent another 20 minutes adding in fancy copper pours and thickening the +3.3V blue trace. The spacing for the AAT101 cap looks fine, but now I've noticed how I've got to be careful not to create shorts when soldering one capacitor adjacent to the BLDCC:

Right I forgot all about those ADn pins. Do I need those? Can they be floating or conviniently connected to the AGND next door?

Oh cool it's like I2C on SPI, presumably to allow communications with up to 4 controllers per CS pin. Wow, Ti really made a chip with low pin utilisation in mind.

It looks like they're internally pulled down, so I probably only have to worry about accidentally shorting PWM_SYNC.

Anyway, this is the size I usually see the board on my 15.6" screen, compared to it's calibrated 1 : 1 scale size:

I think it was a good idea to switch to the single masterpad instead of trying to have 2 more interconnect FPCs. Now I can treat the implementation of Tetrinsic more like a camera module or LCD, whereby the other side of the FPC goes into a standard connector (or soldered). However, looking on AliExpress, it seems that a 0.7mm pitch connector is going to be hard to come by.

This PCB looks cooler when all the vias are installed.

It took a few tries to tweak the location of the "Tetrinsic" text since there's now a row of vias cutting into it:

It's likely fine, as it turns out that this entire thing is about the diameter of a 2 pence coin...

...yet it looks like a city metro when I hide the GNDPlane:

I'm certainly going to need to get a vacuum pen thing because tweezers probably aren't going to suffice.

Starting the grind at 14:30, I found out that you can drag the Fusion 360 tabs out to put them in new windows (see below). This helps loads because I could now view the schematic and PCB side by side.

Then I found out how to change the colours of the layers and opted for ones that were more comfortable to my eyes. I also decided that I was going to have 1 interior signal layer and one GND copper pour. I put the pour under the Top layer to potentially help with heat dissipation from the BLDC controller.

By 16:30, I had gotten some connections onto the BLDC:

It was already starting to look like mounting the MINI-1U module on the back was a great idea. It would take much more space to route out if all components were on the same side. Unfortunately, I had to fint in a via so I had to do a select-and-move-surgery:

What you see above was very nice to see. It's what happens when I join up an incomplete trace. It's now one long trace. In EasyEDA, they'd be seperate entities and so I'd have a lot of complete but segmented traces.

2 crashes later, it's now 20:30 and I've tweaked the masterpad order and have now fully connected the BLDC controller, the IMU and managed to get all but EXP0 (connected to IO0) on analog capable pins (which gives me the most flexibility for implementing features). 

Then I remember about POSITION, which is on the right other side of this masterpad and it needs an analog-capable pin. I just used the last one. After looking at my options, I decided to move the MISO pin over and then have a long trace to POSITION:

After a 30 minute break staring at trees (and imagining they're actually all virtual like I'm wearing a futuristic VR headset), I come back rejuvinated with the goal in mind to make #Leti so that I can work on projects while I stand/walk outside.

At 21:30, I found out how the differental pair worked. While I didn't do this for the ADC inputs, the routes I neded up with seemed close enough to a differential pair anyway. Oh, and I watched this video that helped speed up my tracing workflow:

I thought it was a bit early, but I wanted to give the copper pour feature a go. I selected "Copper pour from outline", cliced the edge of the board and it actually worked. I had to click on the outline, not the pour, to get the inspector to activate, and then I changed the net to GND.

It was 22:30 when I found out that I actually missed the supply connection for the LDO. 8 minutes later, and I'm seeing the real power of this push-pull nature of tracing:

I actually forgot to route this trace after routing a few other ones, and I still miraculously had enough space to place that top via thanks to Fusion 360 pushing things away. EasyEDA would've been a complete ripup of so many traces... might've taken 64 minutes to do that, not sub-4.

At 00:30, I was connecting the last of the airwires. I initially thought I was going to copper-pour the bottom layer too, but there's so many traces that it wouldn't be very useful. Oh and Fusion requires every pad to be linked up; it's not enough to start a line at Pad 62 (top left corner pad) and finish it at Pad 65 (top right corner pad). I even encountered what seemed like a ghost AirWire, but since there was only 1, I could use the QuickRoute feature to fix it. Oh yeah... that QuickRoute feature I was talking about last log. Yeah, because it tries to link every Airwire from the same signal, it usually fails. "Manual Routing" is still a good bit more automatic than EasyEDA Online (Standard Edition) ever was. Anyway, I thickened some traces like VSOLAR and VBLDC and here is the result of 10.5 hours of work:

Here's what everything got connected to on the MINI-1U:

And here's the pinout of the masterpad:

The order of the I2S pins were chosen based on one of Adafruits boards:

Progress update:

Basically, what happened is that I spawned those vias around the BLDC controller to see what kind of space I needed to have for ICs. I extended the PCB 5mm, which gave me loads of room. Looking at the Tetrinsic 3D model, I reduced the PCB by 2mm. Then I moved the backlight circuitry and EN passives so that they were much closer to where they needed to be.

And then I tried this for the very first time:

I was thinking that this was going to have some cool marker where you can drag a dot-to-dot of lines as a placeholder for traces. This is what it actually did:

Have you ever heard that sound effect of explosion magic charging up? That's the sound I was thinking of when what would've been at least 15 seconds in EasyEDA was reduced to 1. And it only took a few minutes to find out that the Unroute commands in the Inspector were the ones that I jumped over to Fusion 360 Electronics in the first place:

For some reason, the Unroute command in the toolbar is rather subpar, basically acting like EasyEDA but I can just click to delete instead of click, delete button, click, delete button.

These 2 commands, QuickRoute Airwire and Unroute Connection, allow me to place a component somewhere, click to see if it's even possible to route, and if not, try again.

Additionally, I rotated this component and all I had to do was press Reroute and an N$23 pad. This would've been an entire event in EasyEDA, first deleting the traces, rotating and then placing them back.

I changed the order of the ADC inputs for better routing, as well as remove a capacitor for the wheatstone bridges to share since they were getting so close that there was probably little difference in 2 vs 1 capacitor.

Oh, and I've still managed to keep the ADC and BLDC controller in a circular pattern around the origin.

Moving on, this is the reason why I should be able to go with a slightly larger PCB:

For something like #Tetent TestCut [gd0139], the effective size isn't really all that different. Speaking of which, the square needed is 100mm now, up from 92mm.

There's also the other benefit of having enough space to put "Tetrinsic" branding here. Reminds me of XILINX FPGA branding:

I know those vias are likely going to fracture the vision of my 17.5mm square ideal, so I thought I'd just get started.

From what I understand, I could go as low as a 0.05mm thick via, but I thought that a good size would be 0.2mm inner : 0.4mm outer. I also looked at JLCPCBs other capabilities and thought "hmm nah, don't chance it) and set all distances to 0.2mm. I've believed that 0.2mm track/spacing is the aim for fabrication that I'm going to persue for #SecSavr Soapavr [gd0146] anyway.

Then I've got to look at these to figure out about the Via spacings:

From this, it kinda seems that I shoud have the same-signal via at 0.1mm (which would be 0.3mm total if measured like JLCPCB) and just have 0.2mm for different signals like everything else.

Now, I was saying that I wanted a 0.4mm diameter via, but it seemed like anything smaller than 0.55mm (Fusion's default smallest) was the exact same size.

this was the setting that I had to change. I think "Pads" in this case refers to through-hole pads, which I don't have on this design.

Now I've got a via that actually looks like 0.4mm.

I had a feeling I was going to have at least one pad that generated to close.

Anyway, back to mentally routing traces before I start drawing some that I'd likely have to wrip up later.

I've already determined the pinouts in the top right corner. I still want to expose IO0 somehow and so I've put it on the extra EXP pin.